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參數(shù)資料
| 型號(hào)： | A8255 |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE PERIPHERAL INTERFACE ADAPTER |
| 中文描述： | 可編程外圍接口適配器 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 250K |
| 代理商： | A8255 |
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Altera Corporation
53
a8255 Programmable Peripheral Interface Adapter Data Sheet
Table 9
shows how the handshaking signals are configured for mode 1
output.
Table 10
summarizes the configuration of port C when both port A and
port B are configured as mode 1.
Note:
(1)
The interrupt enable control bits (
intea
and
inteb
) are stored in the output register bits PC2, PC4, and PC6.
Table 9. Handshaking Signal Configuration (Mode 1 Output)
Name
Signal
Type
Description
nobf
Output
Output buffer full flag. Indicates that data has been written to
the port. Goes low on the rising edge of
nwr
, and returns high
when
nack
is asserted. The rising edge of
nobf
should be
used to latch data into the peripheral.
Acknowledge. Indicates the peripheral is ready to latch the
output data.
Interrupt request. Can be used as the interrupt signal to the
CPU, which indicates that the peripheral device has latched
the data. Reset on the falling edge of
nwr
; set on the rising
edge of
nack
when
inte
is high.
Interrupt enable. Set by bit set to PC6 for port A and PC2 for
port B.
nack
Input
intr
Output
inte
Internal
control
bit
Table 10. Port C with Port A & Port B Both Configured as Mode 1
Note (1)
Bit
Mode 1 Input Mode 1 Output
Description
PC0
PC1
PC2
PC3
PC4
intrb
intrb
Always output.
Always output.
Always input.
Always output.
I/O direction configured by bit 3 of the control register in “mode 1
output.”
I/O direction configured by bit 3 of the control register in “mode 1
output.”
I/O direction configured by bit 3 of the control register in “mode 1
input.”
I/O direction configured by bit 3 of the control register in “mode 1
input.”
ibfb
nobfb
nstbb
nackb
intra
intra
I/O
nstba
PC5
ibfa
I/O
PC6
I/O
nacka
PC7
I/O
nobfa
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