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參數(shù)資料
| 型號(hào)： | A8255 |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE PERIPHERAL INTERFACE ADAPTER |
| 中文描述： | 可編程外圍接口適配器 |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大小： | 250K |
| 代理商： | A8255 |
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48
Altera Corporation
a8255 Programmable Peripheral Interface Adapter Data Sheet
Register Address Map
Table 2
shows the register address map for the
a8255
.
Registers
This section describes the following
a8255
registers:
I
I
Control
Port A, B & C
Control Register
The control register sets the mode and signal direction for the three 8-bit
I/O ports. Control of the I/O ports is split into two groups. Group A
consists of port A and the upper four bits of port C; group B consists of
port B and the lower four bits of port C. Group A can be set to mode 0,
mode 1, or mode 2, but group B can be set to only mode 0 or mode 1.
Writing to the control register address with bit 7 set is the mode definition
format, which allows control of the mode and direction of the three I/O
ports (see
Table 3
). Writing to the control register address with bit 7 reset
is the port C bit set/reset format, which allows single-bit control of port C
(see
Table 4
). The CPU reads the control register using the mode
definition format.
Table 2. Register Address Map
a1
a0
Register
0
0
1
1
0
1
0
1
Port A data (all modes)
Port B data (all modes)
Port C data (mode 0) and status (modes 1 and 2)
Control register mode definition and port C bit set/reset
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