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參數(shù)資料
| 型號： | AD13280 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| 中文描述： | 雙通道，12位，80 MSPS的A / D轉換的模擬輸入信號調(diào)理 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 1353K |
| 代理商： | AD13280 |
REV. 0
AD13280
–10–
or AMP-IN-B-1 when an input of
±
0.5 V full scale is desired. Use
AMP-IN-A-2 or AMP-IN-B-2 when
±
1 V full scale is desired.
Each channel has an AMP-OUT which must be tied to either a
noninverting or inverting input of a differential amplifier with the
remaining input grounded. For example, Side A, AMP-OUT-A
(Pin 6) must be tied to A+IN (Pin 5) with A–IN (Pin 5) tied to
ground for noninverting operation or AMP-OUT-A (Pin 6) tied
to A–IN (Pin 4) with A+IN (Pin 5) tied to ground for inverting
operation.
USING THE DIFFERENTIAL INPUT
Each channel of the AD13280 was designed with two optional
differential inputs, A+IN, A–IN and B+IN, B–IN. The inputs
provide system designers with the ability to bypass the AD8037
amplifier and drive the AD8138 directly. The AD8138 differen-
tial ADC driver can be deployed in either a single-ended or
differential input configuration. The differential analog inputs
have a nominal input impedance of 620
and nominal full-
scale input range of 1.2 V p-p. The AD8138 amplifier drives a
differential filter and the custom analog-to-digital converter. The
differential input configuration provides the lowest even-order
harmonics and signal-to-noise (SNR) performance improvement
of up to 3 dB (SNR = 73 dBFS). Exceptional care was taken in
the layout of the differential input signal paths. The differential
input transmission line characteristics are matched and balanced.
Equal attention to system level signal paths must be provided in
order to realize significant performance improvements.
APPLYING THE AD13280
Encoding the AD13280
The AD13280 encode signal must be a high quality, extremely
low phase noise source, to prevent degradation of performance.
Maintaining 12-bit accuracy at 80 MSPS places a premium on
encode clock phase noise. SNR performance can easily degrade
3 dB to 4 dB with 37 MHz input signals when using a high-jitter
clock source. See Analog Devices’ Application Note AN-501,
“Aperture Uncertainty and ADC System Performance” for
complete details. For optimum performance, the AD13280 must
be clocked differentially. The encode signal is usually ac-coupled
into the ENCODE and
ENCODE
pins via a transformer or
capacitors. These pins are biased internally and require no addi-
tional bias.
Shown below is one preferred method for clocking the AD13280.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD13280 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD13280, and limits the
noise presented to the ENCODE inputs. A crystal clock oscillator
can also be used to drive the RF transformer if an appropriate
limited resistor (typically 100
) is placed in the series with
the primary.
T1-4T
100
0.1 F
ENCODE
ENCODE
AD13280
HSMS2812
DIODES
CLOCK
SOURCE
Figure 6. Crystal Clock Oscillator—Differential Encode
If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input
pins as shown below. A device that offers excellent jitter perfor-
mance is the MC100LVEL16 (or same family) from Motorola.
ENCODE
AD13280
ENCODE
0.1 F
ECL/
PECL
VT
VT
0.1 F
Figure 7. Differential ECL for Encode
Jitter Consideration
The signal-to-noise ratio (SNR) for any ADC can be predicted.
When normalized to ADC codes, Equation 1 accurately predicts
the SNR based on three terms. These are jitter, average DNL
error, and thermal noise. Each of these terms contributes to the
noise within the converter.
f
ANALOG
t
J
RMS
SNR
f
t
V
N
ANALOG
RMS
NOISE RMS
N
2
=
×
+
(
)
+
×
×
×
+
–
log
(
)
/
20
1
2
2
2
2
12
ε
π
J
(1)
=
analog input frequency
= rms jitter of the encode (rms sum of encode
source and internal encode circuitry)
= average DNL of the ADC (typically 0.50 LSB)
= Number of bits in the ADC
V
NOISE RMS
= V rms noise referred to the analog input of the
ADC (typically 5 LSB)
For a 12-bit analog-to-digital converter like the AD13280, aper-
ture jitter can greatly affect the SNR performance as the analog
frequency is increased. The chart below shows a family of curves
that demonstrates the expected SNR performance of the AD13280
as jitter increases. The chart is derived from the above equation.
For a complete discussion of aperture jitter, please consult Ana-
log Devices
’
Application Note AN-501,
“
Aperture Uncertainty
and ADC System Performance.
”
ε
N
CLOCK JITTER
–
ps
0
0
0
1
1
1
2
2
3
3
0
0
1
1
2
2
2
3
3
S
–
–
d
60
A
IN
= 5MHz
A
IN
= 10MHz
A
IN
= 20MHz
A
IN
= 37MHz
61
62
63
64
65
66
67
68
69
70
71
59
58
3
4
Figure 8. SNR vs. Jitter
相關PDF資料 |
PDF描述 |
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| AD13280AF | Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning |
| AD13280AZ | Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning |
| AD13280BZ | Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning |
| AD13465 | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| AD13465AF | Dual Channel, 14-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning |
相關代理商/技術參數(shù) |
參數(shù)描述 |
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| AD13280/PCB | 功能描述:KIT EVAL PCB FOR AD13280 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD13280AF | 功能描述:IC ADC 12BIT 68CLCC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD13280AZ | 功能描述:IC ADC 12BIT 68CLCC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD13280BF | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual-Channel, 12-Bit, 80 MSPS ADC with Analog Input Signal Conditioning |
| AD13280BZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning |
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