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參數(shù)資料
| 型號(hào)： | AD13280 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: RD & RC - Dual Output from a Single Input Rail- 1kVDC & 2kVDC Isolation- Power Sharing on Output- Custom Solutions Available- UL94V-0 Package Material- Efficiency to 86% |
| 中文描述： | 雙通道，12位，80 MSPS的A / D轉(zhuǎn)換的模擬輸入信號(hào)調(diào)理 |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大小： | 1353K |
| 代理商： | AD13280 |
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REV. 0
AD13280
–8–
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE
command and the instant at which the analog input
is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage from the other pin,
which is 180 degrees out of phase. Peak-to-peak differential is
computed by rotating the inputs phase 180 degrees and taking
the peak measurement again. The difference is then computed
between both peak measurements.
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. At a given clock
rate, these specs define an acceptable Encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE
command and the time when all output data bits are
within valid logic levels.
Overvoltage Recovery Time
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc. May be reported
in dB (i.e., degrades as signal level is lowered) or in dBFS
(always related back to converter full scale).
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc. May be reported
in dB (i.e., degrades as signal level is lowered) or in dBFS
(always related back to converter full scale).
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic.
Transient Response
The time required for the converter to achieve 0.02% accuracy
when a one-half full-scale step function is applied to the ana-
log input.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
t
A
A
IN
ENC,
ENC
D[11:0]
DRY
N
N+1
N+2
N+3
N+4
N
N+1
N+2
N+3
N+4
N
–
3
N
–
2
N
–
1
N
t
ENCL
t
ENCH
t
ENC
t
E_DR
t
OD
Figure 1. Timing Diagram
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| AD13280/PCB | 功能描述:KIT EVAL PCB FOR AD13280 RoHS:否 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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| AD13280BZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Channel, 12-Bit, 80 MSPS A/D Converter with Analog Input Signal Conditioning |
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