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參數(shù)資料
| 型號(hào)： | AD1672 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit, 3 MSPS Monolithic A/D Converter(完備的12位單片A/D轉(zhuǎn)換器) |
| 中文描述： | 完整的12位，3 MSPS的單片機(jī)的A / D轉(zhuǎn)換器（完備的12位單片的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 480K |
| 代理商： | AD1672 |
AD1672
REV. 0
–13–
The power dissipated by the correction logic and output buffers
is largely proportional to the clock frequency; running at reduced
clock rates provides a slight reduction in power consumption.
Figure 24 illustrates this tradeoff.
FREQUENCY – MHz
260
252
244
250
248
246
258
256
254
0
5
0.5
P
1
1.5
2
2.5
3
3.5
4
4.5
Figure 24. Typical Power Dissipation vs. Clock Frequency
GROUNDING AND POWER SUPPLY DECOUPLING
RULES
Proper grounding and decoupling should be a primary design
objective in any high speed, high resolution system. The AD1672
features separate analog and digital supply and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, V
CC
, the analog supply, should be de-
coupled to ACOM, the analog common, as close to the chip as
physically possible. Similarly, V
DD
, the digital supply, should be
decoupled to DCOM as close to the chip as physically as pos-
sible. DRV
DD
, the digital supply for the output drivers should
be decoupled to DRCOM which is also connected to the digital
ground plane.
Figure 31, the AD1672/EB evaluation board schematic, demon-
strates the recommended decoupling strategy for the supply
pins. Note that in extremely noisy environments, a more elabo-
rate supply filtering scheme may be necessary. Figure 25 shows
the power supply rejection ratio vs. frequency for 100 mV of
FREQUENCY – MHz
1
10
0.2
S
2
–30
–120
–40
–50
–60
–70
V
CC
V
DD
DRV
DD
–80
–90
–100
–110
0.1
0.5
5
Figure 25. Power Supply Rejection vs. Frequency,
100 mV p-p Signal on Power Supplies
FREQUENCY – MHz
0.1
10
0.2
2
75
65
60
55
40
50
45
70
DRV
DD
V
CC
V
DD
5
1
0.5
S
Figure 26. S/(N+D) vs. Supply Noise Frequency
power supply ripple at various frequencies. Figure 26 shows the
degradation in S/(N+D) ratio resulting from this 100 mV power
supply ripple for a full-scale analog input at 500 kHz. The
AD1672/EB evaluation board was used to generate these graphs
The AD1672 is designed to minimize the code dependent cur-
rent at REFCOM, therefore reducing input dependent analog
ground voltage drops and errors. The majority of code depen-
dent ground current is diverted to ACOM.
The digital activity on the AD1672 chip falls into two general
categories: CMOS correction logic, and CMOS output drivers.
The internal correction logic draws relatively small surges of
current which flow through V
DD
and DCOM. The output
drivers draw large current impulses while the output bits are
changing. The size and duration of these currents is a function
of the load on the output bits: large capacitive loads are to be
avoided. The output drivers are supplied through DRV
DD
and
DRCOM. A 0.1
μ
F ceramic capacitor for decoupling the driver
supply, DRV
DD
, is appropriate for a reasonable capacitive load
on the digital outputs (typically 20 pF on each pin). Applica-
tions involving greater digital loads should consider increasing
the digital decoupling proportionately.
For those applications that require a single +5 V supply for both
the analog and digital supply, a clean analog supply may be
generated using the circuit shown in Figure 27. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained using low ESR
(Equivalent Series Resistance) type electrolytic and tantalum
capacitors.
FERRITE
BEADS
100μF
ELECT.
10–20μF
TANT.
0.1μF
CER.
+5V
AGND
+5V
DGND
+5V
POWER SUPPLY
TTL/CMOS
LOGIC
CIRCUITS
Figure 27. Differential LC Filter for Single +5 V Applications
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