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參數(shù)資料
| 型號(hào)： | AD1853JRSZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STEREO 192KHZ 5V 28SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，I²S，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 200mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 192k |
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REV. A
AD1853
–10–
Control Register
The following table shows the functions of the control register. The control register is addressed by having a “01” in the bottom 2 bits
of the 16-bit SPI word. The top 14 bits are then used for the control register.
Bit 11
Bit 10
Bit 9:8
Bit 7
Bit 6
Bit 5:4
Bit 3:2
INT2
× Mode
INT4
× Mode
Number of
Soft Reset.
Soft Mute OR’d Serial Mode OR’d
De-Emphasis Filter
OR’d with Pin.
Bits in Right-
Default = 0
with Pin.
with Mode Pins.
Select.
Default = 0
Justified Serial
Default = 0
IDPMI:IDPM0
0:0 No Filter
Mode.
0:0 Right-Justified
0:1 44.1 kHz Filter
0:0 = 24
0:1 I
2S
1:0 32 kHz Filter
0:1 = 20
1:0 Left-Justified
1:1 48 kHz Filter
1:0 = 16
1:1 DSP Mode
Default = 0.0
Default = 0:0
Mute
The AD1853 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal HI, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (Bit 6) HI. The AD1853
has been designed to minimize pops and clicks when muting
and unmuting the device by automatically “ramping” the gain
up or down. When the device is unmuted, the volume returns to
the value set in the volume register.
Analog Attenuation
The AD1853 also offers the choice of using IREF (Pin 10) to
attenuate by up to 50 dB in the analog domain. This feature can
be used as an analog volume control. It is also a convenient
place to add a compressor/limiter gain control signal.
Output Drive, Buffering and Loading
The AD1853 analog output stage is able to drive a 1 k
(in
series with 2 nF) load. The analog outputs are usually ac
coupled with a 10
F capacitor.
De-Emphasis
The AD1853 has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
“Redbook” 50
s/15 s emphasis response curve. Three curves
are available; one each for 32 kHz, 44.1 kHz and 48 kHz sam-
pling rates. The external “DEEMP” pin (Pin 9) turns on the
44.1 kHz de-emphasis filter. The other filters may be selected
by writing to control Bits 2 and 3 in the control register. If the
SPI port is used to control the de-emphasis filter, the external
DEEMP pin should be tied LO.
Control Signals
The IDPM0 and IDPM1 control inputs are normally con-
nected HI or LO to establish the operating state of the AD1853.
They can be changed dynamically (and asynchronously to
LRCLK and the master clock), but it is possible that a click
or pop sound may result during the transition from one serial
mode to another. If possible, the AD1853 should be placed in
mute before such a change is made.
Figures 9–14 show the calculated frequency response of the
digital interpolation filters. Figures 15–27 show the performance
of the AD1853 as measured by an Audio Precision System 2
Cascade. For the wideband plots, the noise floor shown in the
plots is higher than the actual noise floor of the AD1853. This is
caused by the higher noise floor of the “High Bandwidth” ADC
used in the Audio Precision measurement system. The two-tone
test shown in Figure 18 is per the SMPTE standard for measur-
ing Intermodulation Distortion.
FREQUENCY – kHz
0.001
0
dB
210
12
14
16
20
0.0008
0.0006
0.0004
0.0002
0
–0.0002
–0.0004
–0.0006
–0.0008
–0.001
46
8
18
Figure 9. Passband Response 8
× Mode, 48 kHz Sample
Rate
FREQUENCY – kHz
0
ATTENUATION
–
dB
–60
–100
–160
–20
–40
–80
–120
–140
0
150
200
50
100
250
300
350
Figure 10. Complete Response, 8
× Mode, 48 kHz
Sample Rate
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD1854JRSZRL | IC DAC STEREO 96KHZ 5V 28SSOP |
| AD1859JRZ-RL | IC DAC STEREO SGL SUPP 5V 28SOIC |
| AD1866RZ-REEL | IC DAC AUDIO DUAL SGL 16SOIC |
| AD1928YSTZ | IC CODEC 2ADC 8DAC W/PLL 48LQFP |
| AD1933WBSTZ-RL | IC DAC 24BIT SRL/SPI 64LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1854 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Stereo, 96 kHz, Multibit DAC |
| AD1854JRS | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:STEREO,96KHZ, MULTIBIT SIGMA DELTA DAC - Bulk |
| AD1854JRSRL | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:STEREO,96KHZ, MULTIBIT SIGMA DELTA DAC - Bulk |
| AD1854JRSZ | 功能描述:IC DAC STEREO 96KHZ 5V 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AD1854JRSZRL | 功能描述:IC DAC STEREO 96KHZ 5V 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
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