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參數(shù)資料
| 型號： | AD1859JRZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 0K |
| 描述： | IC DAC STEREO SGL SUPP 5V 28SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD1859 Discontinuation 12/Apr/2012 |
| 標準包裝： | 1 |
| 位數(shù)： | 18 |
| 數(shù)據(jù)接口： | DSP，I²S，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 330mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD1859JRZ-RLDKR |
a
Stereo, Single-Supply
18-Bit Integrated
DAC
AD1859
PRODUCT OVERVIEW
The AD1859 is a complete 16-/18-bit single-chip stereo digital
audio playback subsystem. It comprises a variable rate digital
interpolation filter, a revolutionary multibit sigma-delta (
∑)
modulator with dither, a jitter-tolerant DAC, switched capacitor
and continuous time analog filters, and analog output drive cir-
cuitry. Other features include an on-chip stereo attenuator and
mute, programmed through an SPI-compatible serial control
port.
The key differentiating feature of the AD1859 is its asynchro-
nous master clock capability. Previous
∑ audio DACs re-
quired a high frequency master clock at 256 or 384 times the
intended audio sample rate. The generation and management
of this high frequency synchronous clock is burdensome to the
board level designer. The analog performance of conventional
single bit
∑ DACs is also dependent on the spectral purity of
the sample and master clocks. The AD1859 has a digital Phase
Locked Loop (PLL) which allows the master clock to be asyn-
chronous, and which also strongly rejects jitter on the sample
clock (left/right clock). The digital PLL allows the AD1859 to
be clocked with a single frequency (27 MHz for example) while
the sample frequency (as determined from the left/right clock)
can vary over a wide range. The digital PLL will lock to the
new sample rate in approximately 100 ms. Jitter components
15 Hz above and below the sample frequency are rejected by
6 dB per octave. This level of jitter rejection is unprecedented
in audio DACs.
The AD1859 supports continuously variable sample rates with
essentially linear phase response, and with an option for external
analog de-emphasis processing. The clock circuit includes an
on-chip oscillator, so that the user need only provide an external
crystal. The oscillator may be overdriven, if desired, with an ex-
ternal clock source.
(continued on page 7)
*SPI is a registered trademark of Motorola, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Complete, Low Cost Stereo DAC System in a Single Die
Package
Variable Rate Oversampling Interpolation Filter
Multibit
Modulator with Triangular PDF Dither
Discrete and Continuous Time Analog Reconstruction
Filters
Extremely Low Out-of-Band Energy
64 Step (1 dB/Step) Analog Attenuator with Mute
Buffered Outputs with 2 k
Output Load Drive
Rejects Sample Clock Jitter
94 dB Dynamic Range, –88 dB THD+N Performance
Option for Analog De-emphasis Processing with
External Passive Components
0.1 Maximum Phase Linearity Deviation
Continuously Variable Sample Rate Support
Digital Phase Locked Loop Based Asynchronous Master
Clock
On-Chip Master Clock Oscillator, Only External Crystal
Is Required
Power-Down Mode
Flexible Serial Data Port (I
2S-Justified, Left-Justified,
Right-Justified and DSP Serial Port Modes)
SPI* Compatible Serial Control Port
Single +5 V Supply
28-Pin SOIC and SSOP Packages
APPLICATIONS
Digital Cable TV and Direct Broadcast Satellite Set-Top
Decoder Boxes
Digital Video Disc, Video CD and CD-I Players
High Definition Televisions, Digital Audio Broadcast
Receivers
CD, CD-R, DAT, DCC, ATAPI CD-ROM and MD Players
Digital Audio Workstations, Computer Multimedia
Products
FUNCTIONAL BLOCK DIAGRAM
SERIAL
CONTROL
INTERFACE
AD1859
16- OR 18-BIT
DIGITAL DATA
INPUT
6
ASYNCHRONOUS
CLOCK/CRYSTAL
DE-EMPHASIS
SWITCH LEFT
COMMON MODE
ANALOG
OUTPUTS
DE-EMPHASIS
SWITCH RIGHT
DE-EMPHASIS
MUTE
ANALOG
SUPPLY
2
REFERENCE
FILTER AND
GROUND
CONTROL
DATA
INPUT
2
3
2
DIGITAL
SUPPLY
POWER
DOWN/RESET
ATTEN/
MUTE
OUTPUT
BUFFER
DAC
VOLTAGE
REFERENCE
MULTIBIT
∑ MODULATOR
VARIABLE RATE
INTERPOLATION
SERIAL
DATA
INTERFACE
ATTEN/
MUTE
OUTPUT
BUFFER
ANALOG
FILTER
DAC
MULTIBIT
∑ MODULATOR
VARIABLE RATE
INTERPOLATION
DPLL/CLOCK
MANAGER
ANALOG
FILTER
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD1860N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860N-J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860N-K | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860R | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD1860R-J | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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