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參數(shù)資料
| 型號： | AD1871YRSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC STEREO 24BIT 96KHZ 28SSOP |
| 標準包裝： | 1,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 96k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極 |
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REV. 0
AD1871
–23–
Single-Ended Mode Enable
The Single-Ended Mode Enable Bits (SEL and SER for left and
right channels, respectively), when set to 1, are used to configure
single-ended input on VINxP and VINxN (input is selected by
state of MXL and MXR). In this mode, single-ended inputs taken
from either VINxP or VINxN (selected using the Mux Select
Bits—MXL and MXR) are internally converted to a differential
format to be applied to the modulator section (see Table XII).
Table XII. Differential/Single-Ended Select
SEL
SER
Input Setting
0X
Left Channel Input
Differential
1X
Left Channel Input
Single-Ended
X0
Right Channel Input
Differential
X1
Right Channel Input
Single-Ended
Master Clock Divider
The master clock divider allows the division of the external
MCLK frequency to a more suitable internal master clock
frequency (IMCLK). IMCLK must be 256
fS; therefore, if
the available MCLK is not at 256
fS but is a multiple of
this, the MCD allows conversion of MCLK to a suitable IMCLK
at 256
fS (see Table XIII).
Table XIII. Master Clock Divider Settings
MCD1
MCD0
MCLK Division
00
IMCLK = MCLK (/1)
01
IMCLK = MCLK/2
10
IMCLK = MCLK/3
11
IMCLK = MCLK (/1)
Table IX. Control Register III (Address 0010b)
15–12
11
10
9
8
7
6
5
4
3
2
1
0
0010
0
MCD1
MCD0
SEL
SER
MEL
MXL
MER
MXR
9–8
Reserved
(Should Be Programmed to 0)
7–6
MCD1–MCD0 Master Clock Divider (See Table XIII)
5
SEL
Single-Ended Enable, Left Channel (0 = Differential (Default); 1 = Single-Ended)
4
SER
Single-Ended Enable, Right Channel (0 = Differential (Default); 1 = Single-Ended)
3
MEL
Mux/PGA Disable, Left Channel (0 = Enabled (Default); 1 = Disabled)
2
MXL
Mux Select, Left Channel (0 = VINLP Selected (Default); 1 = VINLN Selected)
1
MER
Mux/PGA Disable, Right Channel (0 = Enabled (Default); 1 = Disabled)
0
MXR
Mux Select, Right Channel (0 = VINRP Selected (Default); 1 = VINRN Selected)
Control Register III
Control Register III contains bit settings for configuration of the
analog input section (both left and right channels).
Mux Enable
The Mux Enable Left (MEL) and Mux Enable Right (MER)
are used to enable the analog buffers. When these bits are set to
1, the analog input buffers are powered down and input signals
must be applied directly to the modulator inputs via the CAPxP
and CAPxN pins. (see Figure 23). When MEL and MER are set
to 0 (default condition after reset), the analog input section is
enabled, (see Table X).
Table X. Mux Control Settings
MEL
MER
Input Setting
0X
Left Channel Analog Buffer Enabled
1X
Left Channel Analog Buffer Disabled
X0
Right Channel Analog Buffer Enabled
X1
Right Channel Analog Buffer Disabled
Mux Select
The Mux Select Bits (MXL and MXR for left and right channels,
respectively) are used to select the input from VINxP or VINxN
when the input is configured as single-ended. When MXx is set
to 0, the input is taken from VINxP. When MXx is set to 1, the
input is taken from VINxN, (see Table XI).
Table XI. Mux Select Settings
*
MXL
MXR
Input Setting
0X
Left Channel Input from VINLP
1X
Left Channel Input from VINLN
X0
Right Channel Input from VINRP
X1
Right Channel Input from VINRN
*Mux select settings are only valid when single-ended operation is enabled; SEL
and SER are set to 1.
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