參數(shù)資料
型號： AD1871YRSZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 8/28頁
文件大小： 0K
描述： IC ADC STEREO 24BIT 96KHZ 28SSOP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 24
采樣率（每秒）： 96k
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，單極
AD1871
–16–
REV. 0
FUNCTIONAL DESCRIPTION
Clocking Scheme
The MCLK pin is the input for the master clock frequency to
the device. Nominally the MCLK frequency will be 256
fS for
correct operation of the device. However, if the user’s MCLK is
a multiple of 256
fS (perhaps 512 fS or 768 fS), it is possible
to divide down the MCLK frequency to a suitable internal master
clock frequency (IMCLK) using the MCLK divider block as
shown in Figure 8. The divide options can be chosen from pass-
through (/1), /2, or /3 corresponding with 256
fS, 512 fS, or
768
fS MCLKs, respectively. The MCLK divider can be con-
trolled using the MCD1–MCD0 Bits of Control Register III.
(see Table XIII.)
The resulting internal MCLK (IMCLK) is used to run the
decimating and filtering engine and must be chosen to be at a
ratio of 256
fS.
SINC
FILTER
HALF-BAND
FILTERS
IMCLK
/2
/4
12.288MHz/
24.576MHz
6.144MHz
384kHz/
768kHz
48kHz/
96kHz
AMC BIT
(CONT REG I)
0/1
6.144MHz
ANALOG
INPUT
/1
/2
/3
MCLK
DIVIDER
IMCLK
DIVIDER
48kHz/
96kHz
HPE BIT
(CONT REG I)
MODCLK
-
MODULATOR
HIGH-PASS
FILTERS
Figure 8. Clocking Scheme to Modulator and Filter Engine
Modulator
The AD1871’s analog
-
modulator section comprises a
second order multibit implementation using Analog Device’s
proprietary technology for best performance. As shown in
Figure 9, the two analog integrator blocks are followed by a
Flash ADC section that generates the multibit samples. The
output of the Flash ADC, which is thermometer encoded, is decoded
to binary for output to the filter sections and is scrambled for
feedback to the two integrator stages.
The modulator is optimized for operation at a sampling rate
of 6.144 MHz (which is 128
fS at 48 kHz sampling and
64
fS at 96 kHz sampling). The modulator clock control
(AMC Bit in Control Register I) is used to select the modulator
clock (MODCLK) as a ratio from the IMCLK. The modulator
clock divider options are /2 (default) for 48 kHz operation and
/4 for 96 kHz operation. When operating with an IMCLK of
12.288 MHz, the default divider setting (/2) gives a modulator clock
of 6.144 MHz. When operating with an IMCLK of 24.576 MHz,
the alternate divider setting (/4) gives a modulator clock of
6.144 MHz (see Figure 8).
If it is required to operate the device at a different output sample
rate than those detailed above, perhaps 44.1 kHz or 88.2 kHz,
the decimation filter cutoff characteristics can then be determined
from the normalized frequency response plot shown in TPC 6.
FLASH
ADC
SCRAMBLER
THERMO-
METER
TO
BINARY
DECODER
FEEDBACK DACs
FROM
ANALOG
INPUT
SECTION
DIGITAL
OUTPUT
(4 BITS/6.144MHz)
Figure 9. Modulator Block Diagram
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