參數(shù)資料
型號： AD1928YSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 11/32頁
文件大小： 0K
描述： IC CODEC 2ADC 8DAC W/PLL 48LQFP
標準包裝： 1
類型： 通用
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 8
三角積分調(diào)變： 是
S/N 比，標準 ADC / DAC (db)： 94 / 94
動態(tài)范圍，標準 ADC / DAC (db)： 105 / 108
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 托盤
AD1928
Rev. B | Page 19 of 32
DAISY-CHAIN MODE
The AD1928 also allows a daisy-chain configuration to expand
the system to 4 ADCs and 16 DACs (see Figure 18). In this mode,
the DBCLK frequency is 512 fS. The first eight slots of the DAC
TDM data stream belong to the first AD1928 in the chain and
the last eight slots belong to the second AD1928. The second
AD1928 is the device attached to the DSP TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1928 can be configured into a dual-line TDM mode, as
shown in Figure 19. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1928 in the chain and the last four channels belong to
the second AD1928.
The dual-line TDM mode can also be used to send data at a
192 kHz sample rate into the AD1928, as shown in Figure 20.
There are two configurations for the ADC port to work in
daisy-chain mode. The first one is with an ABCLK at 256 fS,
shown in Figure 21. The second configuration is shown in
Figure 22. Note that in the 512 fS ABCLK mode, the ADC
channels occupy the first eight slots; the second eight slots are
empty. The TDM_IN of the first AD1928 must be grounded in
all modes of operation.
The input/output pins of the serial ports are defined according
to the serial mode selected. See Table 13 for a detailed
description of the function of each pin. See Figure 26 for a
typical AD1928 configuration with two external stereo DACs
and two external stereo ADCs.
Figure 23 through Figure 25 show the serial mode formats. For
maximum flexibility, the polarity of LRCLK and BCLK are
programmable. In these figures, all of the clocks are shown with
their normal polarity. The default mode is I2S.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 UNUSED SLOTS
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
MSB
DSDATA1 (TDM_IN)
OF THE SECOND AD1928
DSDATA2 (TDM_OUT)
OF THE SECOND AD1928
THIS IS THE TDM
TO THE FIRST AD1928
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
DSP
SECOND
AD1928
FIRST
AD1928
06
62
3-
0
18
Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two-AD1928 Daisy Chain)
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