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參數(shù)資料
| 型號(hào)： | AD1934WBSTZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8CH W/ON-CHIP PLL 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | * |
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Data Sheet
AD1934
Rev. D | Page 23 of 28
AUXILIARY TDM PORT CONTROL REGISTERS
Table 23. Auxiliary TDM Control 0
Bit
Value
Function
Description
1:0
00
24
Word width
01
20
10
Reserved
11
16
4:2
000
1
SDATA delay (BCLK periods)
001
0
010
8
011
12
100
16
101
Reserved
110
Reserved
111
Reserved
6:5
00
Reserved
Serial format
01
Reserved
10
DAC aux mode
11
Reserved
7
0
Latch in midcycle (normal)
BCLK active edge (TDM in)
1
Latch in at end of cycle (pipeline)
Table 24. Auxiliary TDM Control 1
Bit
Value
Function
Description
0
50/50 (allows 32/24/20/16 BCLK/channel)
LRCLK format
1
Pulse (32 BCLK/channel)
1
0
Drive out on falling edge (DEF)
BCLK polarity
1
Drive out on rising edge
2
0
Left low
LRCLK polarity
1
Left high
3
0
Slave
LRCLK master/slave
1
Master
5:4
00
64
BCLKs per frame
01
128
10
256
11
512
6
0
Slave
BCLK master/slave
1
Master
7
0
AUXTDMBCLK pin
BCLK source
1
Internally generated
ADDITIONAL MODES
The AD1934 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 19 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This configuration
is applicable when the AD1934 master clock is generated by the
PLL with the DLRCLK as the PLL reference frequency.
To relax the requirement for the setup time of the AD1934 in
cases of high speed TDM data transmission, the AD1934 can
latch in the data using the falling edge of DBCLK. This
effectively dedicates the entire BCLK period to the setup time.
This mode is useful in cases where the source has a large delay
time in the serial data driver. Figure 20 shows this pipeline
mode of data transmission.
Both the BLCK-less and pipeline modes are available.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1934YSTZ | 功能描述:IC DAC 8CH W/ON-CHIP PLL 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD1934YSTZ-RL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD1935 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
| AD1935XSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
| AD1935XSTZRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
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