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參數(shù)資料
| 型號(hào)： | AD1934WBSTZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 4/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8CH W/ON-CHIP PLL 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | * |
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AD1934
Data Sheet
Rev. D | Page 12 of 28
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTERS (DACs)
The AD1934 DAC channels are arranged as single-ended, four
stereo pairs giving eight analog outputs for minimum external
components. The DACs include on-board digital reconstruction
filters with 70 dB stop-band attenuation and linear phase response,
operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes)
or 2 (192 kHz mode). Each channel has its own independently
programmable attenuator, adjustable in 255 steps in increments
of 0.375 dB. Digital inputs are supplied through four serial data
input pins (one for each stereo pair) and a common frame
(DLRCLK) and bit (DBCLK) clock. Alternatively, one of the
TDM modes can be used to access up to 16 channels on a single
TDM data line.
Each output pin has a nominal common-mode dc level of 1.5 V
and swings ±1.27 V for a 0 dBFS digital input signal. A single op
amp, third-order, external, low-pass filter is recommended to
remove high frequency noise present on the output pins. The
use of op amps with low slew rate or low bandwidth can cause
high frequency noise and tones to fold down into the audio
band; therefore, exercise care in selecting these components.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
The on-chip phase locked loop (PLL) can be selected to
reference the input sample rate from either of the LRCLK pins
or 256, 384, 512, or 768 times the sample rate, referenced to the
48 kHz mode from the MCLKI pin. The default at power-up is
256 × fS from MCLKI pin. In 96 kHz mode, the master clock
frequency stays at the same absolute frequency; therefore, the
actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if a
device in the AD1934 family is programmed in 256 × fS mode, the
frequency of the master clock input is 256 × 48 kHz = 12.288 MHz.
If the AD1934 is then switched to 96 kHz operation (by writing
to the SPI port), the frequency of the master clock should
remain at 12.288 MHz, which is now 128 × fS. In 192 kHz mode,
this becomes 64 × fS.
The internal clock for the DACs varies by mode: 512 × fS (48 kHz
mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By
default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × fS (referenced to 48 kHz
mode) master clock can be used for DACs if selected in PLL
and Clock Control 1 Register.
The PLL can be powered down in PLL and Clock Control 0
Register. To ensure reliable locking when changing PLL modes,
or if the reference clock is unstable at power-on, power down
the PLL and then power it back up when the reference clock
has stabilized.
The internal MCLK can be disabled in PLL and Clock Control 0
Register to reduce power dissipation when the AD1934 is idle.
The clock should be stable before it is enabled. Unless a stand-
alone mode is selected (see the Serial Control Port section), the
clock is disabled by reset and must be enabled by writing to the
SPI port for normal operation.
To maintain the highest performance possible, it is recommended
that the clock jitter of the internal master clock signal be limited
to less than 300 ps rms time interval error (TIE). Even at these
levels, extra noise or tones can appear in the DAC outputs if the
jitter spectrum contains large spectral peaks. If the internal PLL
is not being used, it is highly recommended that an independent
crystal oscillator generate the master clock. In addition, it is
especially important that the clock signal not be passed through
an FPGA, CPLD, or other large digital chip (such as a DSP)
before being applied to the AD1934. In most cases, this induces
clock jitter due to the sharing of common power and ground
connections with other unrelated digital output signals. When
the PLL is used, jitter in the reference clock is attenuated above
a certain frequency depending on the loop filter.
RESET AND POWER-DOWN
Reset sets all the control registers to their default settings.
To avoid pops, reset does not power down the analog outputs.
After reset is deasserted, and the PLL acquires lock condition,
an initialization routine runs inside the AD1934. This
initialization lasts for approximately 256 MCLKs.
The power-down bits in the PLL and Clock Control 0 and DAC
Control 1 registers power down the respective sections. All
other register settings are retained. To guarantee proper startup,
the reset pin should be pulled low by an external resistor.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD1934YSTZ | 功能描述:IC DAC 8CH W/ON-CHIP PLL 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AD1934YSTZ-RL | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD1935 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
| AD1935XSTZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
| AD1935XSTZRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
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