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參數(shù)資料
| 型號： | AD420AR-32 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC SRL 16BIT 24-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 31 |
| 設(shè)置時間： | 2.5µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 176mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，雙極 |
| 采樣率（每秒）： | 400 |
AD420
Rev. H | Page 10 of 16
APPLICATIONS INFORMATION
CURRENT OUTPUT
The AD420 can provide 4 mA–20 mA, 0 mA–20 mA, or 0 mA–
24 mA output without any active external components. Filter
capacitors C1 and C2 can be any type of low cost ceramic
capacitors. To meet the specified full-scale settling time of 3 ms,
low dielectric absorption capacitors (NPO) are required.
Suitable values are C1 = 0.01 μF and C2 = 0.01 μF.
00
49
4-
0
06
5
2
20
14
15
11
21
23
4
6
18
7
8
9
IOUT (4mA TO 20mA)
RLOAD
VCC
VLL
AD420
GND
0.1F
REF IN
REF OUT
C1
C2
DATA IN
CLOCK
LATCH
CLEAR
RANGE
SELECT 2
RANGE
SELECT 1
Figure 6. Standard Configuration
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads ,connect a 0.01 μF
capacitor between IOUT (Pin 18) and GND (Pin 11). This ensures
stability of the AD420 with loads beyond 50 mH. There is no
maximum capacitance limit. The capacitive component of the
load may cause slower settling, though this may be masked by
the settling time of the AD420. A programmed change in the
current may cause a back EMF voltage on the output that may
exceed the compliance of the AD420. To prevent this voltage
from exceeding the supply rails connect protective diodes
between IOUT and each of VCC and GND.
VOLTAGE-MODE OUTPUT
Since the AD420 is a single supply device, it is necessary to add
an external buffer amplifier to the VOUT pin to obtain a selection
of bipolar output voltage ranges as shown in Figure 7.
00
49
4-
0
7
5
2
20
14
15
11
21
23
4
6
17
7
8
9
VOUT
R2
R3
R1
VCC
VLL
AD420
GND
0.1F
REF IN
REF OUT
C1
C2
DATA IN
CLOCK
LATCH
CLEAR
RANGE
SELECT 2
RANGE
SELECT 1
Figure 7.
Table 7. Buffer Amplifier Configuration
R1
R2
R3
VOUT
Open
0
0 V 5 V
Open
R
Open
R
±5 V
R
2R
±10 V
Suitable R = 5 kΩ.
OPTIONAL SPAN AND ZERO TRIM
For users who would like lower than the specified values of
offset and gain error, Figure 8 shows a simple way to trim these
parameters. Care should be taken to select low drift resistors
because they affect the temperature drift performance of
the DAC.
The adjustment algorithm is iterative. The procedure for
trimming the AD420 in the 4 mA–20 mA mode can be
accomplished as follows:
1.
Offset adjust. Load all zeros. Adjust RZERO for
4.00000 mA of output current.
2.
Gain adjust. Load all ones. Adjust RSPAN for 19.99976 mA
(FS 1 LSB) of output current.
Return to Step I and iterate until convergence is obtained.
00
49
4-
0
08
5
2
20
14
15
16
11
21
23
4
6
18
19
7
8
9
IOUT (4mA TO 20mA)
RLOAD
5k
RSPAN2
500
RSPAN
10k
RZERO
BOOST
VCC
AD420
GND
REF OUT
C1
C2
DATA IN
CLOCK
LATCH
CLEAR
RANGE
SELECT 2
RANGE
SELECT 1
VLL
0.1F
Figure 8. Offset and Gain Adjust
Variation of RZERO between REF OUT (5 V) and GND leads
to an offset adjust range from 1.5 mA to 6 mA, (1.5 mA/V
centered at 1 V).
The 5 kΩ RSPAN2 resistor is connected in parallel with the
internal 40 W sense resistor, which leads to a gain increase of
+0.8%.
As RSPAN is changed to 500 Ω, the voltage on REF IN is
attenuated by the combination of RSPAN and the 30 kΩ REF IN
input resistance. When added together with RSPAN2 this
results in an adjustment range of 0.8% to +0.8%.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD420AR-32 | 制造商:Analog Devices 功能描述:SEMICONDUCTORSLINEAR |
| AD420AR-32-REEL | 功能描述:IC DAC SNGL 16BIT 24-SOIC T/R RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD420ARZ-32 | 功能描述:IC DAC SRL 16BIT 24-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD420ARZ-32-REEL | 功能描述:IC DAC SERIAL INPUT 16BIT 24SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD421 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Loop-Powered 4 mA to 20 mA DAC |
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