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參數(shù)資料
型號(hào): AD5204BRZ50-REEL
廠商: Analog Devices Inc
文件頁數(shù): 18/20頁
文件大?。?/td> 0K
描述: IC DGTL POT QUAD 50K 24-SOIC
標(biāo)準(zhǔn)包裝: 1,000
接片: 256
電阻(歐姆): 50k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 700 ppm/°C
存儲(chǔ)器類型: 易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V,±2.3 V ~ 2.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 帶卷 (TR)
AD5204/AD5206
Rev. C | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC
1
NC
2
GND
3
CS
4
B4
24
W4
23
A4
22
B2
21
PR
5
VDD 6
SHDN
7
W2
20
A2
19
A1
18
SDI
8
W1
17
CLK
9
B1
16
SDO 10
A3
15
VSS 11
W3
14
NC 12
B3
13
AD5204
TOP VIEW
(Not to Scale)
NC = NO CONNECT
06
88
4-
0
06
Figure 6. AD5204 SOIC/TSSOP/PDIP Pin Configuration
Table 3. AD5204 SOIC/TSSOP/PDIP Pin Function Descriptions
Pin No.
Name
Description
1, 2, 12
NC
Not Connected.
3
GND
Ground.
4
CS
Chip Select Input (Active Low). When CS returns high, data in the serial input register is decoded based on the address
bits, and then it is loaded into the target RDAC latch.
5
PR
Preset to Midscale (Active Low). This pin sets the RDAC registers to 0x80.
6
VDD
Positive Power Supply. This pin is specified for operation at both 3 V and 5 V. It is the sum of |VDD| + |VSS| < 5.5 V.
7
SHDN
Terminal A Open-Circuit Shutdown (Active Low Input). This pin controls VR 1 through VR 4.
8
SDI
Serial Data Input. Data is input MSB first.
9
CLK
Serial Clock Input. This pin is positive edge triggered.
10
SDO
Serial Data Output. This pin is an open-drain transistor and requires a pull-up resistor.
11
VSS
Negative Power Supply. This pin is specified for operation at both 0 V and 2.7 V. It is the sum of |VDD| + |VSS| < 5.5 V.
13
B3
Terminal B RDAC 3.
14
W3
Wiper RDAC 3. Address = 0102.
15
A3
Terminal A RDAC 3.
16
B1
Terminal B RDAC 1.
17
W1
Wiper RDAC 1. Address = 0002.
18
A1
Terminal A RDAC 1.
19
A2
Terminal A RDAC 2.
20
W2
Wiper RDAC 2. Address = 0012.
21
B2
Terminal B RDAC 2.
22
A4
Terminal A RDAC 4.
23
W4
Wiper RDAC 4. Address = 0112.
24
B4
Terminal B RDAC 4.
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