參數資料
型號: AD5204BRZ50-REEL
廠商: Analog Devices Inc
文件頁數: 6/20頁
文件大小: 0K
描述: IC DGTL POT QUAD 50K 24-SOIC
標準包裝: 1,000
接片: 256
電阻(歐姆): 50k
電路數: 4
溫度系數: 標準值 700 ppm/°C
存儲器類型: 易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V,±2.3 V ~ 2.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 24-SOIC W
包裝: 帶卷 (TR)
AD5204/AD5206
Rev. C | Page 14 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
VOLTAGE OUTPUT OPERATION
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting Terminal A to 5 V and Terminal B to
ground produces an output voltage at the wiper that can be any
value from 0 V up to 1 LSB less than +5 V. Each LSB of voltage
is equal to the voltage applied across Terminal A and Terminal B
divided by the 256-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to
Terminal A and Terminal B is
VW (Dx) = Dx/256 × VAB + VB
(3)
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. In this
mode, the output voltage is dependent on the ratio of the
internal resistors, not the absolute value; therefore, the drift
improves to 15 ppm/°C.
PR
A1
W1
B1
VDD
CS
CLK
SDO*
D7
D0
RDAC
LATCH
4/6
R
A4/A6
W4/W6
B4/B6
D7
D0
EN
ADDR
DEC
A1
A2
A0
D7
SDI
DO
DI
SER
REG
D0
SHDN*
DGND
8
*AD5204 ONLY
RDAC
LATCH
1
R
AD5204/AD5206
06
88
4-
0
47
Figure 22. Block Diagram
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