參數(shù)資料
型號(hào): AD5235BRU25-RL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 29/32頁(yè)
文件大?。?/td> 0K
描述: IC DGTL POT DUAL 1024POS 16TSSOP
標(biāo)準(zhǔn)包裝: 1
接片: 1024
電阻(歐姆): 25k
電路數(shù): 2
溫度系數(shù): 標(biāo)準(zhǔn)值 35 ppm/°C
存儲(chǔ)器類型: 非易失
接口: 4 線 SPI(芯片選擇)
電源電壓: 3 V ~ 5.5 V,±2.25 V ~ 2.75 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: AD5235BRU25-RL7DKR
AD5235
Data Sheet
Rev. F | Page 6 of 32
INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 k, 250 k VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
measured using both VDD = 2.7 V and VDD = 5 V.
Table 2.
Parameter
Symbol
Conditions
Min
Typ1
Max
Unit
Clock Cycle Time (tCYC)
t1
20
ns
CS Setup Time
t2
10
ns
CLK Shutdown Time to CS Rise
t3
1
tCYC
Input Clock Pulse Width
t4, t5
Clock level high or low
10
ns
Data Setup Time
t6
From positive CLK transition
5
ns
Data Hold Time
t7
From positive CLK transition
5
ns
CS to SDO-SPI Line Acquire
t8
40
ns
CS to SDO-SPI Line Release
t9
50
ns
CLK to SDO Propagation Delay2
t10
RP = 2.2 k, CL < 20 pF
50
ns
CLK to SDO Data Hold Time
t11
RP = 2.2 k, CL < 20 pF
0
ns
CS High Pulse Width3
t12
10
ns
CS High to CS High3
t13
4
tCYC
RDY Rise to CS Fall
t14
0
ns
CS Rise to RDY Fall Time
t15
0.15
0.3
ms
Store EEMEM Time4, 5
t16
Applies to Instructions 0x2, 0x3
15
50
ms
Read EEMEM Time4
t16
Applies to Instructions 0x8, 0x9, 0x10
7
30
s
CS Rise to Clock Rise/Fall Setup
t17
10
ns
Preset Pulse Width (Asynchronous)6
tPRW
50
ns
Preset Response Time to Wiper Setting6
tPRESP
PR pulsed low to refresh wiper positions
30
s
Power-On EEMEM Restore Time6
tEEMEM
30
s
FLASH/EE MEMORY RELIABILITY
Endurance7
TA = 25°C
1
MCycles
100
kCycles
Data Retention8
100
Years
1
Typicals represent average readings at 25°C and VDD = 5 V.
2
Propagation delay depends on the value of VDD, RPULL-UP, and CL.
3
Valid for commands that do not activate the RDY pin.
4
The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 s; CMD_9, CMD_10 ~ 7 s;
CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 s.
5
Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles.
6
7
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 40°C, +25°C, and +85°C.
8
Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
derates with junction temperature in the Flash/EE memory.
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