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參數(shù)資料
| 型號： | AD5301BRTZ-500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 8BIT 2WIRE I2C SOT23-6 |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設置時間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.4mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應商設備封裝： | SOT-23-6 |
| 包裝： | 標準包裝 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 167k |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
| 其它名稱： | AD5301BRTZ500RLDKR |
AD5301/AD5311/AD5321
Rev. B | Page 5 of 24
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
B Version2
Parameter3
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
VDD = 5 V
AD5301
6
8
μs
1/4 scale to 3/4 scale change (0x40 to 0xC0)
AD5311
7
9
μs
1/4 scale to 3/4 scale change (0x100 to 0x300)
AD5321
8
10
μs
1/4 scale to 3/4 scale change (0x400 to 0xC00)
Slew Rate
0.7
V/μs
Major-Code Change Glitch Impulse
12
nV-s
1 LSB change around major carry
Digital Feedthrough
0.3
nV-s
1 See the Terminology section.
2 Temperature range for the B Version is as follows: –40°C to +105°C.
3 Guaranteed by design and characterization, not production tested.
TIMING CHARACTERISTICS1
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Limit at TMIN, TMAX
Parameter2
(B Version)
Unit
Conditions/Comments
fSCL
400
kHz max
SCL clock frequency
t1
2.5
μs min
SCL cycle time
t2
0.6
μs min
tHIGH, SCL high time
t3
1.3
μs min
tLOW, SCL low time
t4
0.6
μs min
tHD,STA, start/repeated start condition hold time
t5
100
ns min
tSU,DAT, data setup time
t63
0.9
μs max
tHD,DAT, data hold time
0
μs min
t7
0.6
μs min
tSU,STA, setup time for repeated start
t8
0.6
μs min
tSU,STO, stop condition setup time
t9
1.3
μs min
tBUF, bus free time between a stop condition and a start condition
t10
300
ns max
0
ns min
May be CMOS driven
t11
250
ns max
300
ns max
20 + 0.1Cb5
ns min
Cb
400
pF max
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization, not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (refer to the VIH MIN of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
4 tR and tF measured between 0.3 VDD and 0.7 VDD.
5 Cb is the total capacitance of one bus line in picofarads.
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
SDA
SCL
t9
t3
t10
t4
t6
t5
t2
t11
t7
t4
t1
t8
00
92
7-
00
2
Figure 2. 2-Wire Serial Interface Timing Diagram
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