參數(shù)資料
型號(hào): AD5301BRTZ-500RL7
廠商: Analog Devices Inc
文件頁數(shù): 7/24頁
文件大?。?/td> 0K
描述: IC DAC 8BIT 2WIRE I2C SOT23-6
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 6µs
位數(shù): 8
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1.4mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6
供應(yīng)商設(shè)備封裝: SOT-23-6
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 167k
產(chǎn)品目錄頁面: 781 (CN2011-ZH PDF)
其它名稱: AD5301BRTZ500RLDKR
AD5301/AD5311/AD5321
Rev. B | Page 15 of 24
WRITE OPERATION
When writing to the AD5301/AD5311/AD5321 DACs, the
user must begin with an address byte, after which the DAC
acknowledges that it is prepared to receive data by pulling
SDA low. This address byte is followed by the 16-bit word in the
form of two control bytes. The write operations for the three
DACs are shown in Figure 29 to Figure 31.
SCL
SDA
SCL
SDA
LEAST SIGNIFICANT CONTROL BYTE
ACK
BY
AD5301
ACK
BY
AD5301
START
COND
BY
MASTER
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
ACK
BY
AD5301
STOP
COND
BY
MASTER
PD1
X
PD0
D7
D6
D5
D4
MOST SIGNIFICANT CONTROL BYTE
ADDRESS BYTE
0A1*
A0
00
11
R/W
D3
D2
D1
D0
X
0
09
27
-02
7
Figure 29. AD5301 Write Sequence
SCL
SDA
SCL
SDA
LEAST SIGNIFICANT CONTROL BYTE
ACK
BY
AD5311
ACK
BY
AD5311
START
COND
BY
MASTER
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
ACK
BY
AD5311
STOP
COND
BY
MASTER
PD1
X
PD0
D9
D8
D7
D6
MOST SIGNIFICANT CONTROL BYTE
ADDRESS BYTE
0A1*
A0
00
11
R/W
D5
D4
D3
D2
D1
D0
X
00
92
7-
0
28
Figure 30. AD5311 Write Sequence
SCL
SDA
SCL
SDA
LEAST SIGNIFICANT CONTROL BYTE
ACK
BY
AD5321
ACK
BY
AD5321
START
COND
BY
MASTER
*THIS BIT MUST BE 0 IN THE 6-LEAD SOT-23 VERSION.
ACK
BY
AD5321
STOP
COND
BY
MASTER
PD1
X
PD0
D11
D10
D9
D8
MOST SIGNIFICANT CONTROL BYTE
ADDRESS BYTE
0A1*
A0
00
11
R/W
D7
D6
D5
D4
D3
D2
D1
D0
00
92
7-
0
29
Figure 31. AD5321 Write Sequence
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