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參數(shù)資料
型號: AD5320BRTZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 17/20頁
文件大?。?/td> 0K
描述: IC DAC 12BIT R-R W/BUFF SOT23-6
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1
設置時間: 8µs
位數(shù): 12
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6
供應商設備封裝: SOT-23-6
包裝: 標準包裝
輸出數(shù)目和類型: 1 電壓,雙極
采樣率(每秒): 125k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
其它名稱: AD5320BRTZ-REEL7DKR-ND
AD5320BRTZREEL7DKR
AD5320
Rev. C | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5320
TOP VIEW
(Not to Scale)
VOUT 1
GND 2
VDD 3
SYNC
SCLK
DIN
6
5
4
009
34-
00
3
Figure 3. SOT-23 Pin Configuration
AD5320
TOP VIEW
(Not to Scale)
VDD 1
NC 2
NC 3
VOUT 4
SYNC
SCLK
DIN
GND
8
7
6
5
009
34-
00
4
NC = NO CONNECT
Figure 4. MSOP Pin Configuration
Table 4. Pin Function Descriptions
SOT-23
Pin No.
MSOP
Pin No.
Mnemonic
Description
1
4
VOUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
2
8
GND
Ground Reference Point for All Circuitry on the Part.
3
1
VDD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and VDD should be decoupled
to GND.
4
7
DIN
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
5
6
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
6
5
SYNC
Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges
of the following clocks. The DAC is updated following the 16th clock cycle unless SYNC is taken high
before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the DAC.
2, 3
NC
No Connect.
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