參數(shù)資料
型號(hào): AD5320BRTZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 3/20頁(yè)
文件大?。?/td> 0K
描述: IC DAC 12BIT R-R W/BUFF SOT23-6
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 8µs
位數(shù): 12
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6
供應(yīng)商設(shè)備封裝: SOT-23-6
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型: 1 電壓,雙極
采樣率(每秒): 125k
產(chǎn)品目錄頁(yè)面: 782 (CN2011-ZH PDF)
其它名稱: AD5320BRTZ-REEL7DKR-ND
AD5320BRTZREEL7DKR
AD5320
Rev. C | Page 11 of 20
THEORY OF OPERATION
D/A SECTION
The AD5320 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Because there is no reference input pin, the
power supply (VDD) acts as the reference. Figure 23 shows a
block diagram of the DAC architecture.
VDD
VOUT
GND
RESISTOR
STRING
REF (+)
REF (–)
OUTPUT
AMPLIFIER
DAC REGISTER
00
93
4-
0
23
Figure 23. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
×
=
4096
D
V
DD
OUT
where D = decimal equivalent of the binary code that is loaded
to the DAC register; it can range from 0 to 4095.
RESISTOR STRING
The resistor string section is shown in Figure 24. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
R
TO OUTPUT
AMPLIFIER
00
93
4-
0
24
Figure 24. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output that gives an output range of 0 V to VDD. It
is capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 11 and Figure 12. The slew rate is 1 V/μs
with a half-scale settling time of 8 μs with the output unloaded.
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