參數(shù)資料
型號(hào)： AD5325ARM
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO10
封裝： MO-187BA, MSOP-10
文件頁(yè)數(shù)： 15/20頁(yè)
文件大小： 427K
代理商： AD5325ARM
REV. F
AD5305/AD5315/AD5325
–15–
DOUBLE-BUFFERED INTERFACE
The AD5305/AD5315/AD5325 DACs have double-buffered
interfaces consisting of two banks of registers—input registers and
DAC registers. The input register is directly connected to the input
shift register and the digital code is transferred to the relevant input
register on completion of a valid write sequence. The DAC
register contains the digital code used by the resistor string.
Access to the DAC register is controlled by the
LDAC
bit. When
the
LDAC
bit is set high, the DAC register is latched and, there-
fore, the input register may change state without affecting the
contents of the DAC register. However, when the
LDAC
bit is
set low, the DAC register becomes transparent and the contents
of the input register are transferred to it.
This is useful if the user requires simultaneous updating of all
DAC outputs. The user may write to three of the input registers
individually and then, by setting the
LDAC
bit low when writing
to the remaining DAC input register, all outputs will update
simultaneously.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that
LDAC
was brought low. Normally, when
LDAC
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5305/AD5315/AD5325,
the part will update the DAC register only if the input register
has been changed since the last time the DAC register was
updated, thereby removing unnecessary digital crosstalk.
POWER-DOWN MODES
The AD5305/AD5315/AD5325 have very low power consump-
tion, dissipating typically 1.5 mW with a 3 V supply and 3 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bits 15 and 14 (PD1
and PD0) of the data byte. Table I shows how the state of the
bits corresponds to the mode of operation of the DAC.
Table I. PD1/PD0 Operating Modes
PD1
PD0
Operating Mode
0
0
1
1
0
1
0
1
Normal Operation
Power-Down (1 k
Load to GND)
Power-Down (100 k
Load to GND)
Power-Down (Three-State Output)
When both bits are set to 0, the DAC works normally with its
normal power consumption of 600
μ
A at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (80 nA at 3 V). Not only does the supply current drop, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has an
advantage in that the output impedance of the part is known
while the part is in power-down mode and provides a defined
input condition for whatever is connected to the output of the
DAC amplifier. There are three different options. The output is
connected internally to GND through either a 1 k
resistor or a
100 k
resistor, or it is left open-circuited (three-state). Resistor
tolerance =
±
20%. The output stage is illustrated in Figure 10.
AMPLIFIER
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
RESISTOR
STRING DAC
V
OUT
Figure 10. Output Stage during Power-Down
The bias generator, the output amplifiers, the resistor string,
and all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
DAC registers are unchanged when in power-down. The time to
exit power-down is typically 2.5
μ
s for V
DD
= 5 V and 5
μ
s
when V
DD
= 3 V. This is the time from the rising edge of the
eighth SCL pulse to when the output voltage deviates from its
power-down voltage. See TPC 18 for a plot.
APPLICATIONS
Typical Application Circuit
The AD5305/AD5315/AD5325 can be used with a wide range
of reference voltages where the devices offer full, one-quadrant
multiplying capability over a reference range of 0 V to V
DD
. More
typically, these devices are used with a fixed, precision reference
voltage. Suitable references for 5 V operation are the AD780 and
REF192 (2.5 V references). For 2.5 V operation, a suitable exter-
nal reference would be the AD589, a 1.23 V band gap reference.
Figure 11 shows a typical setup for the AD5305/AD5315/AD5325
when using an external reference. Note that A0 can be high or low.
AD5305/
AD5315/
AD5325
V
OUT
B
V
OUT
D
GND
SDA
SERIAL
INTERFACE
V
OUT
EXT
REF
0.1 F
V
OUT
A
V
OUT
C
REFIN
AD780/REF192
WITH V
= 5V
OR AD589 WITH
V
DD
= 2.5V
V
DD
= 2.5V TO 5.5V
V
IN
A0
10 F
1 F
SCL
Figure 11. AD5305/AD5315/AD5325 Using External Reference
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