參數(shù)資料
型號(hào)： AD5325ARM
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 12-BIT DAC, PDSO10
封裝： MO-187BA, MSOP-10
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 427K
代理商： AD5325ARM
REV. F
–6–
AD5305/AD5315/AD5325
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
10
9
8
7
6
1
2
3
4
5
V
DD
V
OUT
A
GND
SDA
SCL
V
OUT
D
AD5305/
AD5315/
AD5325
V
OUT
B
V
OUT
C
REFIN
A0
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
V
DD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be
decoupled to GND.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V
DD
.
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit
input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with an
external pull-up resistor.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit
input shift register. Clock rates of up to 400 kbit/s can be accommodated in the 2-wire interface.
Address Input. Sets the least significant bit of the 7-bit slave address.
2
3
4
5
6
7
8
V
OUT
A
V
OUT
B
V
OUT
C
REFIN
V
OUT
D
GND
SDA
9
SCL
10
A0
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus code plots can be seen in TPCs 1, 2, and 3.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of
±
1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in TPCs 4, 5, and 6.
Offset Error
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
Offset Error Drift
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/
°
C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/
°
C.
Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
OUT
to
a change in V
DD
for full-scale output of the DAC. It is measured
in dB. V
REF
is held at 2 V and V
DD
is varied
±
10%.
DC Crosstalk
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in
μ
V.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC out-
put to the reference input when the DAC output is not being
updated. It is expressed in dB.
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