參數(shù)資料
型號： AD5343
廠商： Analog Devices, Inc.
英文描述： 2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
中文描述： 2.5 V至5.5 V，115微安，并行接口單電壓輸出DAC的8-/10-/12-Bit
文件頁數(shù)： 3/20頁
文件大小： 274K
代理商： AD5343
REV. 0
–3–
AD5332/AD5333/AD5342/AD5343
AC CHARACTERISTICS
1
B Version
3
Min
Parameter
2
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
AD5332
AD5333
AD5342
AD5343
Slew Rate
Major Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
V
REF
= 2 V. See Figure 20
1/4 Scale to 3/4 Scale Change (40 H to C0 H)
1/4 Scale to 3/4 Scale Change (100 H to 300 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
6
7
8
8
0.7
6
0.5
3
0.5
3.5
200
–70
8
9
10
10
μ
s
μ
s
μ
s
μ
s
V/
μ
s
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
1 LSB Change Around Major Carry
V
REF
= 2 V
±
0.1 V p-p. Unbuffered Mode
V
REF
= 2.5 V
±
0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology section.
3
Temperature range: B Version: –40
°
C to +105
°
C; typical specifications are at 25
°
C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
Parameter
Limit at T
MIN
, T
MAX
0
0
20
5
4.5
5
5
4.5
5
4.5
20
20
50
20
0
Unit
Condition/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
CS
to
WR
Setup Time
CS
to
WR
Hold Time
WR
Pulsewidth
Data, GAIN, BUF, HBEN Setup Time
Data, GAIN, BUF, HBEN Hold Time
Synchronous Mode.
WR
Falling to
LDAC
Falling
Synchronous Mode.
LDAC
Falling to
WR
Rising
Synchronous Mode.
WR
Rising to
LDAC
Rising
Asynchronous Mode.
LDAC
Rising to
WR
Rising
Asynchronous Mode.
WR
Rising to
LDAC
Falling
LDAC
Pulsewidth
CLR
Pulsewidth
Time Between
WR
Cycles
A0 Setup Time
A0 Hold Time
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and
timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 1.
Specifications subject to change without notice.
(V
DD
= 2.5 V to 5.5 V. R
L
= 2 k
otherwise noted.)
to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
unless
t
4
t
13
t
7
t
14
t
15
CS
WR
DATA,
GAIN,
BUF,
HBEN
LDAC
1
LDAC
2
CLR
1
SYNCHRONOUS
LDAC
UPDATE MODE
2
ASYNCHRONOUS
LDAC
UPDATE MODE
A0
t
1
t
2
t
3
t
5
t
t
8
t
9
t
10
t
11
t
12
Figure 1. Parallel Interface Timing Diagram
(V
DD
= 2.5 V to 5.5 V, All specifications T
MIN
to T
MAX
unless otherwise noted.)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD5343BRU 制造商:Analog Devices 功能描述:DAC 2-CH Resistor-String 12-bit 20-Pin TSSOP 制造商:Analog Devices 功能描述:12BIT DAC DUAL SMD 5343 TSSOP20
AD5343BRU-REEL 制造商:Analog Devices 功能描述:DAC 2-CH Resistor-String 12-bit 20-Pin TSSOP T/R
AD5343BRU-REEL7 制造商:Analog Devices 功能描述:DAC 2-CH Resistor-String 12-bit 20-Pin TSSOP T/R
AD5343BRUZ 功能描述:IC DAC 12BIT DUAL VOUT 20TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF)
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