參數(shù)資料
型號(hào)： AD5381BSTZ-3-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 14/40頁
文件大?。?/td> 0K
描述： IC DAC 12BIT 40CH 3V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5381,3 Redesign Change 24/Oct/2011
設(shè)計(jì)資源： 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010)
AD5381 Channel Monitor Function (CN0013)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 40
電壓電源： 單電源
功率耗散（最大）： 80mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 40 電壓，單極
采樣率（每秒）： 167k
其它名稱： AD5381BSTZ-3-REELDKR
Data Sheet
AD5381
Rev. D | Page 21 of 40
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5381 is a complete, single-supply, 40-channel voltage
output DACthat offers12-bit resolution. The part is available
in a 100-lead LQFP package and features both a parallel and
a serial interface. This product includes an internal, software
selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used
to drive the bufferedreference inputs; alternatively, an external
referencecan be used to drive theseinputs. Internal/external
referenceselection is via the CR8 bit in the control register;
CR10 selects the referencemagnitude if the internal reference
is selected. All channels have an on-chip output amplifier with
rail-to-rail outputcapable of driving 5 k in parallel with a
200 pF load.
03732-027
VOUT
R
12-BIT
DAC
REG
m REG
c REG
×1 INPUT
REG
×2
INPUT DATA
VREF
AVDD
Figure 27. Single-Channel Architecture
The architecture of a single DACchannel consists ofa 12-bit
resistor-string DACfollowed by an outputbuffer amplifier
operating at a gain of 2. This resistor-string architecture
guaranteesDAC monotonicity. The 12-bit binary digital code
loaded to the DAC registerdetermines at whatnode on the
string the voltage is tapped off beforebeing fed to the output
amplifier. Each channel on these devices contains independent
offset and gain control registers that allow theuser to digitally
trim offset and gain. These registers give the userthe ability to
calibrate out errors in the completesignal chain, including the
DAC, using the internal m and cregisters, which hold the
correction factors. All channels are double buffered, allow-
ing synchronous updating of all channels using the LDACpin.
Figure 27 shows a blockdiagram of a single channel on the
AD5381. The digital input transfer function for each DAC
can be represented as
x2 = [(m + 2)/ 2n × x1] + (c – 2n – 1)
where:
x2 = the data-wordloadedto the resistorstring DAC.
x1 = the 12-bit data-wordwritten to the DACinput register.
m = the gain coefficient (default is 0xFFE). The gain coefficient
is written to the 11 most significant bits (DB11 to DB1), the LSB
(DB0)of the data-wordis a 0.
n = DAC resolution (n = 12 for AD5381).
c = the12-bit offset coefficient (default is 0x800).
The complete transfer function for thesedevices can be
represented as
VOUT = 2 × V
REF × x2/2
n
where:
x2 is the data-word loaded to the resistor string DAC. V
REF
is externally applied to the DACREFOUT/REFINpin. For
specified performance, an external reference voltageof 2.5 V is
recommendedfor the AD5381-5, and 1.25 V for the AD5381-3.
DATA DECODING
The AD5381 contains a 12-bit data bus, DB11 to DB0. Depend-
ing on the value of REG1 and REG0 (see Table 10), this data is
loaded into the addressedDACinput registers, offset (c)
registers, or gain (m)registers. The format data, offset (c), and
gain (m) register contents areshown in Table 11 to Table 13.
Table 10. Register Selection
REG1
REG0
Register Selected
1
Input Data Register (x1)
1
0
Offset Register (c)
0
1
Gain Register (m)
0
Special Function Registers (SFRs)
Table 11. DAC Data Format(REG1 = 1, REG0 = 1)
DB11 to DB0
DAC Output (V)
1111
2 V
REF × (4095/4096)
1111
1110
2 V
REF × (4094/4096)
1000
0000
0001
2 V
REF × (2049/4096)
1000
0000
2 V
REF × (2048/4096)
0111
1111
2 V
REF × (2047/4096)
0000
0001
2 V
REF × (1/4096)
0000
0
Table 12. OffsetData Format (REG1 = 1, REG0 = 0)
DB11 to DB0
Offset (LSB)
1111
+2048
1111
1110
+2047
1000
0000
0001
+1
1000
0000
0
0111
1111
–1
0000
0001
–2047
0000
–2048
Table 13. GainData Format(REG1 = 0, REG0 = 1)
DB11 to DB0
Gain Factor
1111
1110
1
1011
1111
1110
0.75
0111
1111
1110
0.5
0011
1111
1110
0.25
0000
0
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