參數(shù)資料
型號(hào)： AD5381BSTZ-3-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/40頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT 40CH 3V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5381,3 Redesign Change 24/Oct/2011
設(shè)計(jì)資源： 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010)
AD5381 Channel Monitor Function (CN0013)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 40
電壓電源： 單電源
功率耗散（最大）： 80mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 40 電壓，單極
采樣率（每秒）： 167k
其它名稱： AD5381BSTZ-3-REELDKR
Data Sheet
AD5381
Rev. D | Page 15 of 40
Mnemonic
Function
REFOUT/REFIN
The AD5381 contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference
output. If the application requires an external reference, it can be applied to this pin and the internal reference can
be disabled via the control register. The default for this pin is a reference input.
VOUT39/MON_OUT
This pin has a dual function. It acts as a buffered output for Channel 39 in default mode. However, when the monitor
function is enabled, this pin acts as the output of a 39-to-1 channel multiplexer that can be programmed to
multiplex one of Channels 0 to 38 to the MON_OUT pin. The MON_OUT pin’s output impedance is typically 500
and is intended to drive a high input impedance like that exhibited by SAR ADC inputs.
SER/PAR
Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. If it is tied high,
the serial interface mode is selected and Pin 97 (SPI/I
2C) is used to determine if the interface mode is SPI or I2C.
Parallel interface mode is selected when SER/PAR is low.
CS/(SYNC/AD0)
In parallel interface mode, this pin acts as chip select input (level sensitive, active low). When low, the AD5381
is selected.
Serial Interface Mode. This is the frame synchronizationinput signal for the serialclock and data.
I2C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address
for the device on the I2C bus.
WR/(DCEN/AD1)
Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a
daisy-chain enable in SPI mode and as a hardware address pin in I2C mode.
Parallel Interface Write Input (edge sensitive). The rising edge of WR is used in conjunction with CS low,and the
address bus inputs to write to the selected device registers.
Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction
with SER/PAR high to enable the SPI serial interface daisy-chain mode.
I2C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address
for this device on the I2C bus.
DB11–DB0
Parallel Data Bus. DB11 is the MSB and DB0 is the LSB of the input data-word onthe AD5381.
A5–A0
Parallel Address Inputs. A5 to A0 are decoded to address one of the AD5381’s 40 input channels. Used in conjunction
with the REG1 and REG0 pins to determine the destination register for the input data.
REG1, REG0
In parallel interface mode, REG1 and REG0 are used in decoding the destination registers for the input data. REG1
and REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and
are also used to decide the special function registers.
SDO/(A/B)
Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a
number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the fallingedge
of SCLK.
When operating in parallel interface mode, this pin acts as the A or B data register select when writing data to the
AD5381’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the
LDAC is used to switch the output between the data contained in the A and B data registers. All DAC channels
contain two data registers. In normal mode, Data Register A is the default for data transfers.
BUSY
Digital CMOS Output. BUSY goes low during internal calculations ofthe data (x2) loaded to the DAC data register.
During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the
DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low,this event is stored.BUSY also
goes low during power-on reset, and when the RESET pin is low.During this time,the interface is disabled andany
events on LDAC are ignored.A CLR operation also brings BUSYlow.
LDAC
Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high),the contents of the input
registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSYis
active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when
BUSY goes inactive. However any events on LDAC during power-on reset or on RESET are ignored.
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive.When CLRis activated,all channels are updated
with the data contained in the CLR code register.BUSY is low for a duration of35 s while all channels are being
updated with the CLR code.
RESET
Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power-
on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1,
m, c, and x2 registers to their default power-on values. This sequence typically takes270 s. The falling edge of RESET
initiates the RESET process and BUSY goes low forthe duration,returning high when RESET is complete.While BUSY
is low, all interfaces are disabled and all LDAC pulses are ignored.When BUSYreturns high,the part resumes normal
operation and the status of the RESET pin is ignored untilthe next falling edge is detected.
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