參數(shù)資料
型號: AD5381BSTZ-3-REEL
廠商: Analog Devices Inc
文件頁數(shù): 8/40頁
文件大小: 0K
描述: IC DAC 12BIT 40CH 3V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: AD5381,3 Redesign Change 24/Oct/2011
設(shè)計資源: 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010)
AD5381 Channel Monitor Function (CN0013)
標(biāo)準(zhǔn)包裝: 1
設(shè)置時間: 6µs
位數(shù): 12
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 40
電壓電源: 單電源
功率耗散(最大): 80mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型: 40 電壓,單極
采樣率(每秒): 167k
其它名稱: AD5381BSTZ-3-REELDKR
AD5381
Data Sheet
Rev. D | Page 16 of 40
Mnemonic
Function
PD
Power-Down (Level Sensitive, Active High). PD is used to place the device in low power mode, where the analog
current consumption is reduced to 2 A and the digital current consumption is reduced to 20 A. In power-down
mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high
impedance output or provides a 100 k load to ground, depending on how the power-down mode is configured.
The serial interface remains active during power-down.
FIFO EN
FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user
to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is
sampled on power-up, and also followinga CLEAR or RESET, to determine if the FIFO is enabled. In either serial or
I2C interface modes, the FIFO EN pin should be tied low.
DB9/(SPI/I
2C)
Multifunction Input Pin. In parallel interface mode, this pin acts as DB9 of the parallel input data-word. In serial
interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/PAR = 1) and
this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB11 is the serial data
(DIN) input.
When serial interface mode is selected (SER/PAR = 1) and this input is high I
2C Mode is selected.
In this mode, DB12 is the serial clock (SCL) input and DB11 is the serial data (SDA) input.
DB10/(SCLK/SCL)
Multifunction Input Pin. In parallel interface mode, this pin acts as DB10 of the parallel input data-word. In serial
interface mode, this pin acts as a serial clock input.
Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the fallingedge of SCLK.
This operates at clock speeds up to 50 MHz.
I2C Mode. In I2C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in
I2C mode is compatible with both 100 kHz and 400 kHz operating modes.
DB11/(DIN/SDA)
Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word.
Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling
edge of SCLK.
I2C Mode. In I2C mode, this pin is the serial data pin (SDA) operating as an open-draininput/output.
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