參數(shù)資料
型號(hào)： AD5382BSTZ-3
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 1/40頁(yè)
文件大小： 0K
描述： IC DAC 14BIT 32CHAN 3V 100LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： Redesign Change 28/Oct/2011
設(shè)計(jì)資源： 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011)
AD5382 Channel Monitor Function (CN0012)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 8µs
位數(shù)： 14
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 32
電壓電源： 單電源
功率耗散（最大）： 65mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤(pán)
輸出數(shù)目和類型： 32 電壓，單極
采樣率（每秒）： 125k
32-Channel, 3 V/5 V, Single-Supply,
14-Bit denseDAC
Data Sheet
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113 2004–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User interfaces:
Parallel
Serial (SPI-/QSPI-/MICROWIRE-/DSP-compatible,
featuring data readback)
I2C-compatible
Robust 6.5 kV HBM and 2 kV FICDM ESD rating
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOAs)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
VOUT0
DAC 0
DAC
REG0
INPUT
REG0
14
m REG0
c REG0
1.25V/2.5V
REFERENCE
POWER-ON
RESET
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
DAC 1
DAC
REG1
INPUT
REG1
14
m REG1
c REG1
VOUT6
DAC 6
DAC
REG6
INPUT
REG6
14
m REG6
c REG6
VOUT7
VOUT8
DAC 7
DAC
REG7
INPUT
REG7
14
m REG7
c REG7
×4
03733-
001
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
INTERFACE
CONTROL
LOGIC
DB13/(DIN/SDA)
DB12/(SCLK/SCL)
DB11/(SPI/I2C)
DB10
A4
A0
REG0
REG1
RESET
BUSY
CLR
MON_IN1
MON_IN2
MON_IN3
MON_IN4
PD
SER/PAR
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO
36-TO-1
MUX
VOUT0………VOUT31
MON_OUT
LDAC
VOUT31
DVDD (×3)
DGND (×3)
AVDD (×4)
AGND (×4)
DAC_GND (×4)
REFGND
REFOUT/REFIN
SIGNAL_GND (×4)
AD5382
DB0
R
Figure 1.
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