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參數(shù)資料
| 型號： | AD5383BSTZ-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 32CH 5V 100-LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5381,3 Redesign Change 24/Oct/2011 |
| 設計資源： | 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5383 (CN0014) AD5383 Channel Monitor Function (CN0015) |
| 標準包裝： | 1 |
| 設置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 32 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 65mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極；32 電壓，雙極 |
| 采樣率（每秒）： | 167k |
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AD5383
Data Sheet
Rev. C | Page 22 of 40
ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)
The AD5383 contains a number of special function registers
(SFRs), as outlined in Table 14. SFRs are addressed with
REG1 = REG0 = 0 and are decoded using Address Bit A4 to
Address Bit A0.
Table 14. SFR Register Functions (REG1 = 0, REG0 = 0)
R/W
A4
A3
A2
A1
A0
Function
X
0
NOP (No Operation)
0
1
Write CLR Code
0
1
0
Soft CLR
0
1
0
Soft Power-Down
0
1
0
1
Soft Power-Up
0
1
0
Control Register Write
1
0
1
0
Control Register Read
0
1
0
1
0
Channel Monitor
0
1
Soft Reset
SFR COMMANDS
NOP (No Operation)
REG1 = REG0 = 0, A4 to A0 = 00000
Performs no operation but is useful in serial readback mode to
clock out data on DOUT for diagnostic purposes. BUSY pulses
low during a NOP operation.
Write CLR Code
REG1 = REG0 = 0, A4 to A0 = 00001
DB11 to DB0 = contain the CLR data
Bringing the CLR line low or exercising the soft clear function
loads the contents of the DAC registers with the data con-tained
in the user configurable CLR register, and sets VOUT0 to VOUT31
accordingly. This can be very useful for setting up a specific
output voltage in a clear condition. It is also beneficial for
calibration purposes; the user can load full scale or zero scale to
the clear code register and then issue a hardware or software
clear to load this code to all DACs, removing the need for
individual writes to each DAC. Default on power-up is all zeros.
Soft CLR
REG1 = REG0 = 0, A4 to A0 = 00010
DB11 to DB0 = don’t care
Executing this instruction performs the CLR, which is functionally
the same as that provided by the external CLR pin. The DAC
outputs are loaded with the data in the CLR code register. It
takes 35 s to fully execute the SOFT CLR, as indicated by
the BUSY low time.
Soft Power-Down
REG1 = REG0 = 0, A4 to A0 = 01000
DB11 to DB0 = don’t care
Executing this instruction performs a global power-down
feature that puts all channels into a low power mode that
reduces the analog supply current to 2 A max, and the digital
current to 20 A. In power-down mode, the output amplifier
can be configured as a high impedance output or provide a
100 k load to ground. The contents of all internal registers are
retained in power-down mode. No register can be written to
while in power-down.
Soft Power-Up
REG1 = REG0 = 0, A4 to A0 = 01001
DB11 to DB0 = don’t care
This instruction is used to power up the output amplifiers and
the internal reference. The time to exit power-down is 8 s. The
hardware power-down and software function are internally
combined in a digital OR function.
Soft RESET
REG1 = REG0 = 0, A4 to A0 = 01111
DB11 to DB0 = don’t care
This instruction is used to implement a software reset. All
internal registers are reset to their default values, which
correspond to m at full scale and c at zero scale. The contents of
the DAC registers are cleared, setting all analog outputs to 0 V.
The soft reset activation time is 135 s.
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