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| 型號： | AD5383BSTZ-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 32CH 5V 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5381,3 Redesign Change 24/Oct/2011 |
| 設(shè)計(jì)資源： | 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5383 (CN0014) AD5383 Channel Monitor Function (CN0015) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 32 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 65mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極；32 電壓，雙極 |
| 采樣率（每秒）： | 167k |
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AD5383
Data Sheet
Rev. C | Page 14 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESET
DB5
DB4
DB3
DB2
DB1
DB0
NC
REG0
REG1
VOUT23
VOUT22
VOUT21
VOUT20
AVDD3
AGND3
DAC_GND3
SIGNAL_GND3
VOUT19
VOUT18
VOUT17
VOUT16
AVDD2
AGND2
59
74
75
69
70
71
72
67
68
66
73
64
65
60
61
62
63
57
58
55
56
53
54
52
51
NC
V
OUT
5
V
OUT
6
V
OUT
7
NC
MON_IN1
MON_IN2
MON_IN3
MON_IN4
NC
MON_OUT
V
OUT
8
V
OUT
9
V
OUT
10
V
OUT
11
V
OUT
12
DAC_GND2
SIGNAL_GND2
V
OUT
13
V
OUT
14
V
OUT
15
26
28
27
29
30
32
33
34
35
36
31
37
38
39
40
42
43
44
45
41
46
47
48
49
50
CS/(SYNC/AD0)
DB11/(DIN/SDA)
DB10/(SCLK/SCL)
DB9/(SPI/I
2
C)
DB8
DB7
DB6
SDO(A/B)
DV
DD
DGND
NC
A4
A3
A2
A1
A0
DV
DD
DV
DD
DGND
SER/PAR
PD
WR
(DCEN/AD1)
LDAC
BUSY
100
98
99
97
96
95
94
92
91
90
89
88
87
93
86
85
84
82
81
80
79
78
77
76
83
5
4
3
2
7
6
9
8
1
14
13
12
11
16
15
17
10
19
18
23
22
21
20
24
25
FIFO EN
CLR
VOUT24
VOUT25
VOUT26
VOUT27
SIGNAL_GND4
DAC_GND4
AGND4
AVDD4
VOUT28
VOUT29
VOUT30
VOUT31
REF GND
REFOUT/REFIN
SIGNAL_GND1
DAC_GND1
AVDD1
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
AGND1
PIN 1
IDENTIFIER
AD5383
TOP VIEW
(Not to Scale)
03734-008
Figure 8. 100-Lead LQFP Pin Configuration
Table 9. Pin Function Descriptions
Mnemonic
Function
VOUTx
Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a
gain of 2. Each output is capable of driving an output load of 5 k to ground. Typical output impedance is 0.5 .
SIGNAL_GND(1 to 4)
Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together
internally and should be connected to the AGND plane as close as possible to the AD5383.
DAC_GND(1 to 4)
Each Group of Eight Channels Contains a DAC_GND Pin. This is the ground reference point for the internal 12-bit
DAC. These pins should be connected to the AGND plane.
AGND(1 to 4)
Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be
connected externally to the AGND plane.
AVDD(1 to 4)
Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are connected together
internally and should be decoupled with a 0.1 F ceramic capacitor and a 10 F tantalum capacitor. Operating
range for the AD5383-5 is 4.5 V to 5.5 V; operating range for the AD5383-3 is 2.7 V to 3.6 V.
DGND
Ground for All Digital Circuitry.
DVDD
Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled
with 0.1 F ceramic and 10 F tantalum capacitors to DGND.
REF GND
Ground Reference Point for the Internal Reference.
REFOUT/REFIN
The AD5383 Contains a Common REFOUT/REFIN Pin. When the internal reference is selected, this pin is the
reference output. If the application requires an external reference, it can be applied to this pin and the internal
reference can be disabled via the control register. The default for this pin is a reference input.
MON_OUT
MON_OUT Monitor Output Pin. When the monitor function is enabled, this output acts as the output of a 36-to-1
channel multiplexer that can be programmed to multiplex one of Channels 0 to 31or any of the monitor input pins
(MON_IN1 to MON_IN4) to the MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 , and is
intended to drive a high input impedance like that exhibited by SAR ADC inputs.
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