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參數(shù)資料
| 型號： | AD5398BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT CURRENT-SINK 8LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 250µs |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 8-LFCSP-VD（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電流，單極 |
| 采樣率（每秒）： | 31k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
| 其它名稱： | AD5398BCPZ-REEL7DKR |
AD5398
Rev. B | Page 12 of 16
05034-017
PD
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
00
SCL
SDA
START BY
MASTER
ACK BY
AD5398
11
91
ACK BY
AD5398
ACK BY
AD5398
STOP BY
MASTER
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
FRAME 2
MOST SIGNIFICANT
DATA BYTE
FRAME 1
SERIAL BUS
ADDRESS BYTE
0
1
X
R/W
9
Figure 19. Write Operation
05034-018
PD
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
00
SCL
SDA
START BY
MASTER
ACK BY
AD5398
11
91
ACK BY
AD5398
ACK BY
AD5398
STOP BY
MASTER
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
FRAME 2
MOST SIGNIFICANT
DATA BYTE
FRAME 1
SERIAL BUS
ADDRESS BYTE
0
1
X
R/W
9
Figure 20. Read Operation
Table 7. Data Format
1
Serial Data-Words
High Byte
Low Byte
Serial Data Bits
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Input Register
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
Function
PD
X
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
1 PD = soft power-down; X = unused/don’t care; D9 to D0 = DAC data.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in an application, it is beneficial to
consider power supply and ground return layout on the PCB.
The PCB for the AD5398 should have separate analog and
digital power supply sections. Where shared AGND and DGND
is necessary, the connection of grounds should be made at only
one point, as close as possible to the AD5398.
Special attention should be paid to the layout of the AGND
return path and track between the voice coil motor and ISINK to
minimize any series resistance. Figure 21 shows the output
current sink of the AD5398 and illustrates the importance of
reducing the effective series impedance of AGND, and the track
resistance between the motor and ISINK. The voice coil is
modelled as inductor LC and resistor RC. The current through
the voice coil is effectively a dc current that results in a voltage
drop, VC, when the AD5398 is sinking current; the effect of any
series inductance is minimal. The maximum voltage drop
allowed across RSENSE is 400 mV, and the minimum drain to
source voltage of Q1 is 200 mV. This means that the AD5398
output has a compliance voltage of 600 mV. If VDROP falls below
600 mV, the output transistor, Q1, can no longer operate
properly and ISINK might not be maintained as a constant.
05034-019
7
AGND
VG
Q1
GROUND
RESISTANCE
GROUND
INDUCTANCE
8
ISINK
RSENSE
3.3
Ω
RG
LG
VDROP
VT
VC
VBAT
RT
RC
LC
TRACE
RESISTANCE
VOICE
COIL
ACTUATOR
Figure 21. Effect of PCB Trace Resistance and Inductance
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