All input signals are specified with tr = tf = 1 ns (10" />
參數(shù)資料
型號: AD5424YRUZ
廠商: Analog Devices Inc
文件頁數(shù): 26/29頁
文件大?。?/td> 0K
描述: IC DAC 8BIT MULTIPLYING 16-TSSOP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 96
設置時間: 30ns
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 25µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 20.4M
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
配用: EVAL-AD5424EBZ-ND - BOARD EVALUATION FOR AD5424
Data Sheet
AD5424/AD5433/AD5445
Rev. D | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V; temperature range for Y version: 40°C to +125°C; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
VDD = 2.5 V to 5.5 V
VDD = 4.5 V to 5.5 V
Unit
Test Conditions/Comments
t1
0
ns min
R/W to CS setup time
t2
0
ns min
R/W to CS hold time
t3
10
ns min
CS low time (write cycle)
t4
6
ns min
Data setup time
t5
0
ns min
Data hold time
t6
5
ns min
R/W high to CS low
t7
9
7
ns min
CS min high time
t8
20
10
ns typ
Data access time
40
20
ns max
t9
5
ns typ
Bus relinquish time
10
ns max
1
Guaranteed by design, not subject to production test.
03160-002
CS
DATA
R/W
t1
t2
t6
t7
t8
t2
t9
t3
t4
t5
DATA VALID
Figure 2. Timing Diagram
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