參數(shù)資料
型號(hào)： AD5530BRU
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： ECONOLINE: RO & RE - Industry Standard Pinout- 1kVDC & 2kVDC Isolation- UL94V-0 Package Material- Toroidal Magnetics- Fully Encapsulated- Custom Solutions Available- Efficiency to 85%
中文描述： SERIAL INPUT LOADING, 20 us SETTLING TIME, 12-BIT DAC, PDSO16
封裝： MO-153AB, TSSOP-16
文件頁(yè)數(shù)： 11/16頁(yè)
文件大?。?/td> 407K
代理商： AD5530BRU
REV. 0
AD5530/AD5531
–11–
REFIN
REFAGND
V
OUT
GND
DUTGND
AD5530/
AD5531
*
V
OUT
V
SS
AD586
SIGNAL
GND
C1
1 F
SIGNAL
GND
–
15V
V
OUT
(
–
2
6
5
4
8
*
ADDITIONAL PINS OMITTED FOR CLARITY
+15V
R1
10k
Figure 5. Bipolar
±
10 V Operation
2 REFIN
–2 REFIN
D
0V
DAC INPUT CODE 000 001
(3)FFF
Figure 6. Output Voltage vs. DAC Input Codes (Hex)
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5530/AD5531 is via a serial
bus that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5530/AD5531 requires a
16-bit data word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update may be done
automatically when all the data is clocked in or asynchronously
under the control of
LDAC
.
The contents of the DAC register may be read using the readback
function.
RBEN
is used to frame the readback data, which is
clocked out on SDO. The following figures illustrate these DACs
interfacing with a simple 4-wire interface. The serial interface of
the AD5530/AD5531 may be operated from a minimum of
three wires.
AD5530/AD5531 to ADSP-21xx
An interface between the AD5530/AD5531 and the ADSP-21xx
is shown in Figure 7. In the interface example shown, SPORT0
is used to transfer data to the DAC. The SPORT control regis-
ter should be configured as follows: internal clock operation,
alternate framing mode; active low framing signal.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the
LDAC
pin via the DSP. Alternatively,
the
LDAC
input could be tied permanently low and then the
update takes place automatically when TFS is taken high.
AD5530/
AD5531
*
SCLK
SDIN
SYNC
TFS
DT
SCLK
ADSP-2101/
ADSP-2103
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
LDAC
FO
Figure 7. AD5530/AD5531 to ADSP-21xx Interface
AD5530/AD5531 to 8051 Interface
A serial interface between the AD5530/AD5531 and the 8051 is
shown in Figure 8. TXD of the 8051 drives SCLK of the AD5530/
AD5531, while RXD drives the serial data line, SDIN. P3.3 and
P3.4 are bit-programmable pins on the serial port and are used
to drive
SYNC
and
LDAC
respectively.
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user will have to ensure that the data in the
SBUF register is arranged correctly as the DAC expects MSB first.
AD5530/
AD5531
*
SCLK
SDIN
SYNC
P3.3
RXD
TXD
80C51/80L51
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
LDAC
P3.4
Figure 8. AD5530/AD5531 to 8051 Interface
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RXD is clocked out of the microcontroller on the rising
edge of TXD and is valid on the falling edge. As a result no glue
logic is required between this DAC and microcontroller interface.
The 8051 transmits data in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. As the DAC expects a
16-bit word, P3.3 must be left low after the first 8 bits are transferred.
After the second byte has been transferred, the P3.3 line is taken
high. The DAC may be updated using
LDAC
via P3.4 of the 8051.
AD5530/AD5531 to MC68HC11 Interface
Figure 9 shows an example of a serial interface between the
AD5530/AD5531 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the DAC, while the MOSI
output drives the serial data lines, SDIN.
SYNC
is driven from
one of the port lines, in this case PC7.
AD5530/
AD5531
*
SCLK
SDIN
SYNC
PC7
MOSI
SCK
MC68HC11
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
LDAC
PC6
Figure 9. AD5530/AD5531 to MC68HC11 Interface
相關(guān)PDF資料
PDF描述
AD5531 Serial Input, Voltage Output 12-/14-Bit DACs
AD5531BRU RE Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 05V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85%
AD5532 32-Channel, 14-Bit Voltage-Output DAC
AD5532-1 32-Channel, 14-Bit Voltage-Output DAC
AD5532-2 32-Channel, 14-Bit Voltage-Output DAC
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