參數(shù)資料
型號: AD5530BRU
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: ECONOLINE: RO & RE - Industry Standard Pinout- 1kVDC & 2kVDC Isolation- UL94V-0 Package Material- Toroidal Magnetics- Fully Encapsulated- Custom Solutions Available- Efficiency to 85%
中文描述: SERIAL INPUT LOADING, 20 us SETTLING TIME, 12-BIT DAC, PDSO16
封裝: MO-153AB, TSSOP-16
文件頁數(shù): 12/16頁
文件大小: 407K
代理商: AD5530BRU
REV. 0
–12–
AD5530/AD5531
The 68HC11 is configured for master mode, MSTR= 1,
CPOL = 0, and CPHA = 1. When data is transferred to the part,
PC7 is taken low and data is transmitted MSB first. Data appear-
ing on the MOSI output is valid on the falling edge of SCK. Eight
falling clock edges occur in the transmit cycle, so in order to load
the required 16-bit word, PC7 is not brought high until the second
8-bit word has been transferred to the DAC
s input shift register.
LDAC
is controlled by the PC6 port output. The DAC can be
updated after each 2-byte transfer by bringing
LDAC
low. This
example does not show other serial lines for the DAC. If
CLR
were used, it could be controlled by port output PC5. In order to
read data back from the DAC register, the SDO line could be
connected to MISO of the MC68HC11, with
RBEN
tied to another
port output controlling and framing the readback data transfer.
APPLICATIONS
Optocoupler Interface
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in excess
of 3 kV. The serial loading structure of the AD5530/AD5531
makes it ideal for opto-isolated interfaces as the number of
interface lines is kept to a minimum. Figure 10 shows a 4- channel
isolated interface to the AD5530/AD5531. To reduce the
number of opto-isolators, if simultaneous updating is not re-
quired, then the
LDAC
pin may be tied permanently low.
V
CC
TO SDIN
TO SCLK
TO
SYNC
SYNC OUT
SERIAL CLOCK OUT
SERIAL DATA OUT
CONTROLLER
OPTOCOUPLER
TO
LDAC
CONTROL OUT
Figure 10. Opto-Isolated Interface
Serial Interface to Multiple AD5530s or AD5531s
Figure 11 shows how the
SYNC
pin is used to address multiple
AD5530/AD5531s. All devices receive the same serial clock and
serial data, but only one device will receive the
SYNC
signal at any
one time. The DAC addressed will be determined by the decoder.
There will be some feedthrough from the digital input lines, the
effects of which can be minimized by using a burst clock.
ENABLE
DECODER
*
DGND
EN
CODED
ADDRESS
V
CC
AD5530/AD5531
*
SYNC
SDIN
SCLK
V
OUT
AD5530/AD5531
*
SYNC
SDIN
SCLK
V
OUT
AD5530/AD5531
*
SYNC
SDIN
SCLK
V
OUT
AD5530/AD5531
*
SYNC
SDIN
SCLK
V
OUT
SCLK
SDIN
*
ADDITIONAL PINS
OMITTED FOR CLARITY
Figure 11. Addressing Multiple AD5530/AD5531s
Daisy-Chaining Interface with Multiple AD5530s or AD5531s
A number of these DAC parts may be daisy-chained together
using the SDO pin. Figure 12 illustrates such a configuration.
AD5530/AD5531
*
SYNC
SDIN
SCLK
SDO
AD5530/AD5531
*
SYNC
SDIN
SCLK
SDO
AD5530/AD5531
*
SYNC
SDIN
SCLK
SDO
R
R
R
V
DD
SYNC
SDIN
SCLK
TO OTHER
SERIAL DEVICES
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. Daisy-Chaining Multiple AD5530/AD5531s
相關(guān)PDF資料
PDF描述
AD5531 Serial Input, Voltage Output 12-/14-Bit DACs
AD5531BRU RE Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 05V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85%
AD5532 32-Channel, 14-Bit Voltage-Output DAC
AD5532-1 32-Channel, 14-Bit Voltage-Output DAC
AD5532-2 32-Channel, 14-Bit Voltage-Output DAC
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