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參數(shù)資料
| 型號(hào)： | AD5544BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT SER QUAD 32-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 設(shè)置時(shí)間： | 900ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 1.25mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
AD5544/AD5554
Data Sheet
Rev. G | Page 18 of 24
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ a compact, minimum lead length
layout design. The leads to the input should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic
capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capaci-
tors should also be applied at VDD to minimize any transient
disturbance and filter any low frequency ripple (see Figure 26).
Users should not apply switching regulators for VDD due to the
power supply rejection ratio (PSRR) degradation over frequency.
AGNDX
VSS
DGND
AD5544/AD5554
0
09
43-
03
2
VDD
C3
10F
+
C1
0.1F
C4
10F
C2
0.1F
VSS
VDD
Figure 26. Power Supply Bypassing and Grounding Connection
GROUNDING
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 26).
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