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參數(shù)資料
| 型號： | AD5560JSVUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 43/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DPS PROGRAMABLE W/DAC 64TQFP |
| 設計資源： | Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130) |
| 標準包裝： | 1,500 |
| 類型： | 電源 |
| 應用： | 自動測試設備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應商設備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
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AD5560
Data Sheet
Rev. D | Page 48 of 68
Table 19. DPS Register 2
Address
Default
Data Bits, MSB First
0x3
0x0000
Bit
Name
Function
15
SF0
System force and sense line addressing, SF0. Bit SF0 addresses each of the different
combinations of switching the system force and sense lines to the force and sense pins at the
DUT.
Guard High-Z
(Bit 7)
SFO
SYS_SENSE Pin
SYS_FORCE Pin
GUARD/SYS_DUTGND Pin
0
Open
Guard
0
1
Sense
Force
Guard
1
0
Open
1
Sense
Force
DUTGND
14
13
12
SR[2:0]
Slew rate control, SR2, SR1, SR0. Selects the slew rate for the main DAC output amp.
SR
Action
0
1 V/μs
1
0.875 V/μs
2
0.75 V/μs
3
0.62 V/μs
4
0.5 V/μs
5
0.43 V/μs
6
0.35 V/μs
7
0.3125 V/μs
11
GPO
General purpose output bit. The GPO bit can be used for any function, such as disconnecting
the decoupling capacitor to help speed up low current testing.
10
9
SLAVE,
GANGIMODE
Ganging multiple devices increases the current drive available. Use these bits to enable
selection of the ganging mode and place the device in slave or master mode. In default
operation, each device is a master (gang of one). Figure 54 shows how the device is configured
in this mode.
SLAVE
Action
0
Master: MASTER_OUT = internally connects to active EXTFORCE1/
EXTFORCE2 output
1
Master: MASTER_OUT = master MI
2
SLAVE FV to EXTFORCE1/EXTFORCE2 connected internally to close the
FVAMP loop
3
SLAVE FI
8
INT10K
Setting this bit high allows the user to connect an internal sense short resistor of 10 kΩ
between the force and the sense lines (closes SW11). This resistor is actually made up of series
4 kΩ resistors followed by a 2 kΩ switch and another 4 kΩ resistor. There is a 10 kΩ resistor that
can be connected between the FORCE and SENSE pins by use of SW11. This 10 kΩ resistor is
intended to maintain a force/sense connection when a DUT is not in place. It is not intended
to be connected when measurements are being made because this defeats the purpose of the
OSD circuit in identifying an open circuit between FORCE and SENSE. In addition, the sense
path has a 2.5 kΩ resistor in series; therefore, if the 10 kΩ switch is closed, errors may become
apparent when in high current ranges.
7
Guard high-Z
Set this bit high to high-Z the guard amplifier. This is required if using the GUARD/
SYS_DUTGND pin in the SYS_DUTGND function.
6:0
Unused
Set to 0.
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