參數(shù)資料
型號(hào)： AD5590BBC
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/44頁(yè)
文件大?。?/td> 0K
描述： IC ADC I/O PORT16 W/AMP 80CSPBGA
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 12.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 80-CSP-BGA（10x10）
包裝： 托盤
輸入數(shù)目和類型： 16 個(gè)單端，單極
AD5590
Rev. A | Page 28 of 44
ADC Transfer Function
The output coding of the ADC is either straight binary or twos
complement, depending on the status of the LSB (range bit) in
the ADC control register. The designed code transitions occur
midway between successive LSB values (that is, 1 LSB, 2 LSBs,
and so on). The LSB size is equal to VREFA/4096. The ideal transfer
characteristic for the ADC when straight binary coding is selected
is shown in Figure 57.
111...111
111...110
111...000
000...010
011...111
000...001
000...000
0V
1LSB
+VREF – 1LSB
1LSB = VREF/4096
VREF IS EITHER VREFA OR 2 × VREFA
ANALOG INPUT
0
76
91
-0
57
Figure 57. Straight Binary Transfer Characteristic
011...111
011...110
000...001
000...000
111...111
100...010
100...001
100...000
+VREFA – 1LSB
–VREFA + 1LSB
1LSB = 2 × VREFA/4096
VREFA – 1LSB
ANALOG INPUT
AD
C
CO
DE
0
769
1-
0
58
Figure 58. Twos Complement Transfer Characteristic with
VREFA ± VREFA Input Range
Analog Input Selection
Any one of 16 analog input channels can be selected for conversion
by programming the multiplexer with the ADD3 to ADD0
address bits in the ADC control register. The channel configura-
tions are shown in Table 23. The ADC can also be configured to
automatically cycle through a number of channels as selected.
The sequencer feature is accessed via the SEQ and shadow bits
in the ADC control register (see Table 21). The ADC can be
programmed to continuously convert on a selection of channels
in ascending order. The analog input channels to be converted
on are selected through programming the relevant bits in the
shadow register (see Table 26). The next serial transfer then acts
on the sequence programmed by executing a conversion on the
lowest channel in the selection.
The next serial transfer results in a conversion on the next
highest channel in the sequence, and so on. It is not necessary
to write to the ADC control register once a sequencer operation
has been initiated. The write bit must be set to 0 to ensure
the ADC control register is not accidentally overwritten, or
the sequence operation interrupted. If the ADC control register
is written to at any time during the sequence, then it must be
ensured that the SEQ and shadow bits are set to 1 and 0,
respectively to avoid interrupting the automatic conversion
sequence. This pattern continues until the ADC is written to
and the SEQ and shadow bits are configured with any bit
combination except 1, 0. On completion of the sequence, the
ADC sequencer returns to the first selected channel in the shadow
register and commence the sequence again if uninterrupted.
Rather than selecting a particular sequence of channels, a number
of consecutive channels beginning with Channel 0 can also be
programmed via the control register alone, without needing
to write to the shadow register. This is possible if the SEQ and
shadow bits are set to 1, 1. The channel address bits, ADD3
through ADD0, then determine the final channel in the consec-
utive sequence. The next conversion is on Channel 0, then
Channel 1, and so on until the channel selected via the ADD3
through ADD0 address bits is reached. The cycle begins again
on the next serial transfer provided the write bit is set to low
or, if high, that the SEQ and shadow bits are set to 1, 0; then,
the ADC continues its preprogrammed automatic sequence
uninterrupted. Regardless of which channel selection method
is used, the 16-bit word output from the ADC during each
conversion always contains the channel address that the conver-
sion result corresponds to, followed by the 12-bit conversion
result (see the Serial Interface section).
Digital Inputs
The digital inputs applied to the ADC are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V and are not restricted
by the ADCVDD + 0.3 V limit found on the analog inputs.
Another advantage of ASCLK, ADIN, and ASYNC not being
restricted by the ADCVDD + 0.3 V limit is the fact that power
supply sequencing issues are avoided. If ASYNC, ADIN, or
ASCLK is applied before ADCVDD, there is no risk of latch-up
as there would be on the analog inputs if a signal greater than
0.3 V was applied prior to ADCVDD.
VDRIVE
The ADC has the VDRIVE feature, which controls the voltage at
which the serial interface operates. VDRIVE allows the ADC to
easily interface to both 3 V and 5 V processors. For example, if
the ADC is operated with a VDD of 5 V, the VDRIVE pin could be
powered from a 3 V supply. The ADC has better dynamic perfor-
mance with a VDD of 5 V while still being able to interface to 3 V
processors. Care should be taken to ensure that VDRIVE does not
exceed ADCVDD by more than 0.3 V (see the Absolute Maximum
Ratings section).
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