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參數(shù)資料
| 型號： | AD5664BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大小： | 0K |
| 描述： | IC DAC NANO 16BIT QUAD 10-LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 223k |
| 產(chǎn)品目錄頁面： | 783 (CN2011-ZH PDF) |
| 配用： | EVAL-AD5664REBZ-ND - BOARD EVALUATION FOR AD5664R |
| 其它名稱： | AD5664BCPZ-REEL7DKR |
AD5624/AD5664
Rev. 0 | Page 19 of 24
MICROPROCESSOR INTERFACING
AD5624/AD5664 to Blackfin ADSP-BF53x Interface
Figure 35 shows a serial interface between the AD5624/AD5664 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous serial
ports, SPORT1 and SPORT0, for serial and multiprocessor commu-
nications. Using SPORT0 to connect to the AD5624/AD5664, the
setup for the interface is as follows. DTOPRI drives the DIN pin of
the AD5624/AD5664, while TSCLK0 drives the SCLK of the part.
The SYNC is driven from TFS0.
AD5624/
AD56641
ADSP-BF53x1
SYNC
TFS0
DIN
DTOPRI
SCLK
TSCLK0
1ADDITIONAL PINS OMITTED FOR CLARITY.
05
94
3-
0
38
Figure 35. Blackfin ADSP-BF53x Interface to AD5624/AD5664
AD5624/AD5664 to 68HC11/68L11 Interface
Figure 36 shows a serial interface between the AD5624/AD5664
and the 68HC11/68L11 microcontroller. SCK of the 68HC11/
68L11 drives the SCLK of the AD5624/AD5664, while the
MOSI output drives the serial data line of the DAC.
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows.
The 68HC11/68L11 is configured with its CPOL bit as a 0 and
its CPHA bit as a 1. When data is being transmitted to the DAC,
the SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 10-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5624/AD5664,
PC7 is left low after the first eight bits are transferred, and a
second serial write operation is performed to the DAC; PC7 is
taken high at the end of this procedure.
AD5624/
AD56641
68HC11/68L111
SYNC
PC7
SCLK
SCK
DIN
MOSI
1ADDITIONAL PINS OMITTED FOR CLARITY.
05
94
3-
0
3
9
Figure 36. 68HC11/68L11 Interface to AD5624/AD5664
AD5624/AD5664 to 80C51/80L51 Interface
Figure 37 shows a serial interface between the AD5624/AD5664
and the 80C51/80L51 microcontroller. The setup for the interface
is as follows. TxD of the 80C51/80L51 drives SCLK of the
AD5624/AD5664, while RxD drives the serial data line of the
part. The SYNC signal is derived from a bit-programmable pin
on the port. In this case, port line P3.3 is used. When data is
transmitted to the AD5624/AD5664, P3.3 is taken low. The
80C51/80L51 transmits data in 10-bit bytes only; thus only eight
falling clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted, and
a second write cycle is initiated to transmit the second byte of
data. P3.3 is taken high following the completion of this cycle.
The 80C51/80L51 output the serial data in a format that has the
LSB first. The AD5624/AD5664 must receive data with the MSB
first. The 80C51/80L51 transmit routine should take this into
account.
AD5624/
AD56641
80C51/80L511
SYNC
P3.3
SCLK
TxD
DIN
RxD
1ADDITIONAL PINS OMITTED FOR CLARITY.
05
94
3-
0
4
0
Figure 37. 80C51/80L51 Interface to AD5624/AD5664
AD5624/AD5664 to MICROWIRE Interface
Figure 38 shows an interface between the AD5624/AD5664 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and is clocked into the
AD5624/AD5664 on the rising edge of the SK.
AD5624/
AD56641
MICROWIRE1
SYNC
CS
SCLK
SK
DIN
SO
1ADDITIONAL PINS OMITTED FOR CLARITY.
05
94
3-
0
4
1
Figure 38. MICROWIRE Interface to AD5624/AD5664
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