參數(shù)資料
型號: AD569JPZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 12/12頁
文件大?。?/td> 0K
描述: IC DAC 16BIT MONO NON-LIN 28PLCC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 750
設(shè)置時間: 4µs
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.51x11.51)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
AD569
REV. A
–9–
Figure 13. Low-Cost
±5 V Tracking Reference
a. Bandwidth
b. Phase Shift
Figure 14. Full Power Multiplying Performance
a. Time Domain
b. Frequency Domain
Figure 15. Multiplying Mode Performance (Input Code
0001H)
MULTIPLYING PERFORMANCE
Figure 14 illustrates the gain and phase characteristics of the
AD569 when operated in the multiplying mode. Full-power
bandwidth is shown in Figure 14a and the corresponding phase
shift is shown in Figure 14b. Performance is plotted for both a
full-scale input of FFFFH and an input of 8080H. An input rep-
resents worst-case conditions because it places the buffer taps at
the midpoints of both dividers. Figure 15 illustrates the
AD569’s ability to resolve 16-bits (where 1 LSB is 96 dB below
full scale) while keeping the noise floor below –130 dB with an
ac reference of 1 V rms at 200 Hz.
Multiplying feedthrough is due to capacitive coupling between
the reference inputs and the output. As shown in Figure 16,
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