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參數(shù)資料
| 型號： | AD569JPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT MONO NON-LIN 28PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 設(shè)置時間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
AD569
REV. A
–11–
a. Simple Interface
b. Fast Interface
Figure 20. 8-Bit Microprocessor Interface
8-Bit Microprocessor Interfaces
Since 8-bit microprocessors require two write cycles to provide
the AD569’s 16-bit input, the DAC register must be utilized. It
is most often loaded as the second byte enters the first rank of
latches. This synchronous load method, shown in Figure 20, re-
quires LDAC to be tied to either LBE or HBE, depending upon
the byte loading sequence. In either case, the propagation delay
through the first rank gives rise to longer timing requirements as
shown in Figure 2. If the DAC register (LDAC) is controlled
separately using a third write cycle, the minimum write pulse on
LDAC
is 70 ns, as shown in Figure 1.
Two basic methods exist for interfacing the AD569 to an 8-bit
microprocessor’s address and control buses. In either case, at
least one address line is needed to differentiate between the up-
per and lower bytes of the first rank (HBE and LBE). The sim-
plest method involves applying the two addresses directly to
HBE
and LBE and strobing the data using CS as shown in Fig-
ure 20a. However, the minimum pulse width on CS is 70 ns
with a minimum data setup time of 60 ns. If operation with a
shorter pulse width is required, the base address should be ap-
plied to CS with an address line gated with the strobe signal to
supply the HBE and LBE inputs (see Figure 20b). However,
since the write pulse sees a propagation delay, the data still must
remain valid at least 20 ns after the rising edge of the delayed
write pulse.
OUTPUT SETTLING
The AD569’s output buffer amplifier typically settles to within
±0.001% FS of its final value in 3 s for a 10 V step. Figure 21
shows settling for negative and positive full-scale steps with no
load applied. Capable of sourcing or sinking 5 mA, the output
buffer can also drive loads of 1 k
and 1000 pF without loss of
stability. Typical settling to 0.001% under these worst-case con-
ditions is 4
s, and is guaranteed to be a maximum of 6 s. The
plots of Figure 21 were generated using the settling test proce-
dure developed specifically for the AD569.
Subranging 16-Bit ADC
The subranging ADC shown in Figure 22 completes a conver-
sion in less than 20
s, including the sample-hold amplifier’s
sample time. The sample-hold amplifier is allocated 5
s to
settle to 16 bits.
Before the first flash, the analog input signal is routed through
the AD630 at a gain of +1. The lower AD7820 quantizes the
signal to the 8-bit level within 1.4
s, and the 8-bit result is
routed to the AD569 via a digital latch which holds the 8-bit
word for the AD569 and the output logic.
The AD569’s reference polarity is reversed so that a full-scale
output is –5 V and zero scale is 0 V, thereby subtracting an 8-bit
approximation from the original sampled signal. The residue
from the analog subtraction is then quantized by the second 8-
bit flash conversion to recover the 8 LSBs. Even though only the
AD569’s upper 8 MSBs are used, the AD569’s accuracy de-
fines the A/D converter’s overall accuracy. Any errors are di-
rectly reflected in the output.
a. Turn-On Settling
b. Turn-Off Settling
Figure 21. Full-Scale Output Settling
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