- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8892 > AD5735ACPZ (Analog Devices Inc)IC DAC QUAD VOLT CUR 64-LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD5735ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC QUAD VOLT CUR 64-LFCSP |
| 標準包裝： | 1 |
| 設(shè)置時間： | 18µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，4 電壓 |
| 采樣率（每秒）： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
Data Sheet
AD5735
Rev. C | Page 33 of 48
Gain Register
The 12-bit gain register allows the user to adjust the gain of
each channel in steps of 1 LSB. To write to the gain register of
one DAC channel, set the DREG[2:0] bits to 010 (see Table 14).
To write the same gain code to all four DAC channels at the
same time, set the DREG[2:0] bits to 011. The gain register
coding is straight binary, as shown in Table 15. The default code
in the gain register is 0xFFFF. The maximum recommended
gain trim is approximately 50% of the programmed range to
maintain accuracy (for more information, see the Digital Offset
and Gain Control section).
Offset Register
The 12-bit offset register allows the user to adjust the offset
of each channel by 2048 LSB to +2047 LSB in steps of 1 LSB.
To write to the offset register of one DAC channel, set the
DREG[2:0] bits to 100 (see Table 16). To write the same offset
code to all four DAC channels at the same time, set the DREG[2:0]
bits to 101. The offset register coding is straight binary, as shown in
Table 17. The default code in the offset register is 0x8000, which
results in zero offset programmed to the output (for more infor-
mation, see the Digital Offset and Gain Control section).
Clear Code Register
The 12-bit clear code register allows the user to set the clear
value of each channel. To configure a channel to be cleared
when the CLEAR pin is activated, set the CLR_EN bit in the
DAC control register for that channel (see Table 24). To write
to the clear code register, set the DREG[2:0] bits to 110 (see
Table 18). The default clear code is 0x0000 (for more informa-
tion, see the Asynchronous Clear section).
Table 14. Programming the Gain Register
R/W
DUT_AD1
DUT_AD0
DREG2
DREG1
DREG0
DAC_AD1
DAC_AD0
D15 to D4
D3 to D0
0
Device address
0
1
0
DAC channel address
Gain adjustment
1111
Table 15. Gain Register Bit Descriptions
Gain Adjustment
G15
G14
G13 to G5
G4
G3 to G0
+4096 LSB
1
111111111
1
1111
+4095 LSB
1
111111111
0
1111
…
1111
1 LSB
0
000000000
1
1111
0 LSB
0
000000000
0
1111
Table 16. Programming the Offset Register
R/W
DUT_AD1
DUT_AD0
DREG2
DREG1
DREG0
DAC_AD1
DAC_AD0
D15 to D4
D3 to D0
0
Device address
1
0
DAC channel address
Offset adjustment
0000
Table 17. Offset Register Bit Descriptions
Offset Adjustment
OF15
OF14
OF13
OF12 to OF5
OF4
OF3 to OF0
+2047 LSB
1
11111111
1
0000
+2046 LSB
1
11111111
0
0000
…
0000
No Adjustment (Default)
1
0
00000000
0
0000
…
0000
2047 LSB
0
00000000
1
0000
2048 LSB
0
00000000
0
0000
Table 18. Programming the Clear Code Register
R/W
DUT_AD1
DUT_AD0
DREG2
DREG1
DREG0
DAC_AD1
DAC_AD0
D15 to D4
D3 to D0
0
Device address
1
0
DAC channel address
Clear code
0000
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD5044BRUZ | IC DAC QUAD 14BIT SPI 16TSSOP |
| MS3454W24-22S | CONN RCPT 4POS JAM NUT W/SCKT |
| ADV7125JSTZ330 | IC DAC VIDEO 3CH 330MHZ 48LQFP |
| VE-21N-MY-F2 | CONVERTER MOD DC/DC 18.5V 50W |
| LTC2625IGN#PBF | IC DAC 12BIT R-R OCT 16SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5735ACPZ-REEL7 | 功能描述:IC DAC QUAD VOLT CUR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD5737 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad Channel, 16-Bit, Serial Input, 4-20mA Output DAC, Dynamic Power Control, HART Connectivity |
| AD5737_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output |
| AD5737ACPZ | 功能描述:IC DAC QUAD 12BIT CUR 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5737ACPZ-RL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad-Channel, 12-Bit, Serial Input, 4 mA to 20 mA Output |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。