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參數(shù)資料
| 型號： | AD573KNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SAR REGISTER 20DIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 50k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極 |
AD573
–3–
ABSOLUTE MAXIMUM RATINGS
V+ to Digital Common . . . . . . . . . . . . . . . . . . . . . 0 V to +7 V
V– to Digital Common . . . . . . . . . . . . . . . . . . . 0 V to –16.5 V
Analog Common to Digital Common . . . . . . . . . . . . . . .
±1 V
Analog Input to Analog Common . . . . . . . . . . . . . . . . .
±15 V
Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V+
Digital Outputs (High Impedance State) . . . . . . . . . . 0 V to V+
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW
FUNCTIONAL DESCRIPTION
A block diagram of the AD573 is shown in Figure 1. The posi-
tive CONVERT pulse must be at least 500 ns wide. DR goes
high within 1.5
s after the leading edge of the convert pulse
indicating that the internal logic has been reset. The negative
edge of the CONVERT pulse initiates the conversion. The in-
ternal 10-bit current output DAC is sequenced by the integrated
injection logic (I
2L) successive approximation register (SAR)
from its most significant bit to least significant bit to provide an
output current which accurately balances the input signal cur-
rent through the 5 k
resistor. The comparator determines
whether the addition of each successively weighted bit current
causes the DAC current sum to be greater or less than the input
current; if the sum is more, the bit is turned off. After testing all
bits, the SAR contains a 10-bit binary code which accurately
represents the input signal to within 1/2 LSB (0.05% of full scale).
The SAR drives DR low to indicate that the conversion is com-
plete and that the data is available to the output buffers. HBE
and LBE can then be activated to enable the upper 8-bit and
lower 2-bit buffers as desired. HBE and LBE should be brought
high prior to the next conversion to place the output buffers in
the high impedance state.
The temperature compensated buried Zener reference provides
the primary voltage reference to the DAC and ensures excellent
stability with both time and temperature. The bipolar offset in-
put controls a switch which allows the positive bipolar offset
current (exactly equal to the value of the MSB less 1/2 LSB) to
be injected into the summing (+) node of the comparator to
offset the DAC output. Thus the nominal 0 V to +10 V unipolar
input range becomes a –5 V to +5 V range. The 5 k
thin-film
input resistor is trimmed so that with a full-scale input signal, an
input current will be generated which exactly matches the DAC
output with all bits on.
BURIED ZENER REF
COMP-
ARATOR
ANALOG
IN
DB9
HIGH
BYTE
10-BIT
CURRENT
OUTPUT
DAC
V+
V–
DIGITAL
COMMON
CONVERT
INT
CLOCK
10-BIT
SAR
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
HBE
LBE
MSB
LSB
LOW
BYTE
ANALOG
COMMON
BIPOLAR
OFFSET
CONTROL
DATA
READY
AD573
5k
Figure 1. Functional Block Diagram
UNIPOLAR CONNECTION
The AD573 contains all the active components required to per-
form a complete A/D conversion. Thus, for many applications,
all that is necessary is connection of the power supplies (+5 V
and –12 V to –15 V), the analog input and the convert pulse.
However, there are some features and special connections which
should be considered for achieving optimum performance. The
functional pinout is shown in Figure 2.
The standard unipolar 0 V to +10 V range is obtained by short-
ing the bipolar offset control pin (Pin 16) to digital common
(Pin 17).
REV. B
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