參數(shù)資料
型號(hào)： AD5781ARUZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/28頁(yè)
文件大?。?/td> 0K
描述： IC DAC 18BIT SRL 20TSSOP
產(chǎn)品變化通告： AD57x1 Feature Change 27/Jul/2011
設(shè)計(jì)資源： 18-Bit Accurate, low noise, precision bipolar DC voltage source (CN0177)
標(biāo)準(zhǔn)包裝： 1,000
設(shè)置時(shí)間： 1µs
位數(shù)： 18
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： *
采樣率（每秒）： 1M
AD5781
Data Sheet
Rev. D | Page 20 of 28
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
only if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used, and SYNC must be taken high
after the final clock to latch the data. The first falling edge of
SYNC starts the write cycle. Exactly 24 falling clock edges must
be applied to SCLK before SYNC is brought high again. If
SYNC is brought high before the 24th falling SCLK edge, the
data written is invalid. If more than 24 falling SCLK edges are
applied before SYNC is brought high, the input data is also
invalid. The input shift register is updated on the rising edge of
SYNC. For another serial transfer to take place, SYNC must be
brought low again. After the end of the serial data transfer, data
is automatically transferred from the input shift register to the
addressed register. Once the write cycle is complete, the output
can be updated by taking LDAC low while SYNC is high.
Readback
The contents of all the on-chip registers can be read back via
the SDO pin. Table 8 outlines how the registers are decoded.
After a register has been addressed for a read, the next 24 clock
cycles clock the data out on the SDO pin. The clocks must be
applied while SYNC is low. When SYNC is returned high, the
SDO pin is placed in tristate. For a read of a single register, the
NOP function can be used to clock out the data. Alternatively,
if more than one register is to be read, the data of the first
register to be addressed can be clocked out at the same time the
second register to be read is being addressed. The SDO pin
must be enabled to complete a readback operation. The SDO
pin is enabled by default.
HARDWARE CONTROL PINS
Load DAC Function (LDAC)
After data has been transferred into the input register of the
DAC, there are two ways to update the DAC register and DAC
output. Depending on the status of both SYNC and LDAC, one
of two update modes is selected: synchronous DAC updating or
asynchronous DAC updating.
Synchronous DAC Update
In this mode, LDAC is held low while data is being clocked into
the input shift register. The DAC output is updated on the rising
edge of SYNC.
Asynchronous DAC Update
In this mode, LDAC is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC.
Reset Function (RESET)
The AD5781 can be reset to its power-on state by two means:
either by asserting the RESET pin or by utilizing the software
RESET control function (see Table 14). If the RESET pin is not
used, it should be hardwired to IOVCC.
Asynchronous Clear Function (CLR)
The CLR pin is an active low clear that allows the output to be
cleared to a user defined value. The 18-bit clear code value is
programmed to the clearcode register (see Table 13). It is
necessary to maintain CLR low for a minimum amount of time
to complete the operation (see Figure 2). When the CLR signal
is returned high, the output remains at the clear value (if LDAC
is high) until a new value is loaded to the DAC register. The
output cannot be updated with a new value while the CLR pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see Table 14).
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