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參數(shù)資料
| 型號(hào)： | AD5781ARUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 18BIT SRL 20TSSOP |
| 產(chǎn)品變化通告： | AD57x1 Feature Change 27/Jul/2011 |
| 設(shè)計(jì)資源： | 18-Bit Accurate, low noise, precision bipolar DC voltage source (CN0177) |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 1µs |
| 位數(shù)： | 18 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | 1M |
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AD5781
Data Sheet
Rev. D | Page 22 of 28
Control Register
The control register controls the mode of operation of the AD5781.
Table 11. Control Register
MSB
LSB
DB23
DB22
DB21
DB20
DB19...DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R/
W
Register address
Control register data
R/
W
0
1
0
Reserved
LIN COMP
SDODIS
BIN/2sC
DACTRI
OPGND
RBUF
Reserved
Table 12. Control Register Functions
Clearcode Register
The clearcode register sets the value to which the DAC output is set when the CLR pin or CLR bit is asserted. The output value depends
on the DAC coding that is being used, either binary or twos complement. The default register value is 0.
Table 13. Clearcode Register
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB2
DB1
DB0
R/W
Register address
Clearcode register data
R/W
0
1
18-bits of data
X1
1
X is don’t care.
Function
Description
Reserved
These bits are reserved and should be programmed to zero.
RBUF
Output amplifier configuration control.
0: internal amplifier, A1, is powered up and resistors RFB and R1 are connected in series as shown in Figure 52. This allows
an external amplifier to be connected in a gain of two configurations. See the AD5781 Features section for further details.
1: (default) internal amplifier, A1, is powered down and resistors RFB and R1 are connected in parallel as shown in Figure 51
so that the resistance between the RFB and INV pins is 3.4 k, equal to the resistance of the DAC. This allows the RFB and INV
pins to be used for input bias current compensation for an external unity gain amplifier. See the AD5781 Features section
for further details.
OPGND
Output ground clamp control.
0: DAC output clamp to ground is removed, and the DAC is placed in normal mode.
1: (default) DAC output is clamped to ground through a ~6 k resistance, and the DAC is placed in tristate mode.
Resetting the part puts the DAC in OPGND mode, where the output ground clamp is enabled and the DAC is tristated.
Setting the OPGND bit to 1 in the control register overrules any write to the DACTRI bit
DACTRI
DAC tristate control.
0: DAC is in normal operating mode.
1: (default) DAC is in tristate mode.
BIN/2sC
DAC register coding select.
0: (default) DAC register uses twos complement coding.
1: DAC register uses offset binary coding.
SDODIS
SDO pin enable/disable control.
0: (default) SDO pin is enabled.
1: SDO pin is disabled (tristate).
LIN COMP
Linearity error compensation for varying reference input spans. See the AD5781 Features section for further details.
0
(Default) reference input span up to 10 V.
1
0
Reference input span of 20 V.
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