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| 型號： | AD5781ARUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 18BIT SRL 20TSSOP |
| 產(chǎn)品變化通告： | AD57x1 Feature Change 27/Jul/2011 |
| 設計資源： | 18-Bit Accurate, low noise, precision bipolar DC voltage source (CN0177) |
| 標準包裝： | 1,000 |
| 設置時間： | 1µs |
| 位數(shù)： | 18 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | 1M |
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AD5781
Data Sheet
Rev. D | Page 24 of 28
AD5781 FEATURES
POWER-ON TO 0 V
The AD5781 contains a power-on reset circuit that, as well as
resetting all registers to their default values, controls the output
voltage during power-up. Upon power-on, the DAC is placed in
tristate (its reference inputs are disconnected), and its output is
clamped to AGND through a ~6 kΩ resistor. The DAC remains
in this state until programmed otherwise via the control
register. This is a useful feature in applications where it is
important to know the state of the DAC output while it is in the
process of powering up.
CONFIGURING THE AD5781
After power-on, the AD5781 must be configured to put it into
normal operating mode before programming the output. To do
this, the control register must be programmed. The DAC is
removed from tristate by clearing the DACTRI bit, and the
output clamp is removed by clearing the OPGND bit. At this
point, the output goes to VREFN unless an alternative value is first
programmed to the DAC register.
DAC OUTPUT STATE
The DAC output can be placed in one of three states, controlled
by the DACTRI and OPGND bits of the control register, as
shown in Table 16.
Table 16. AD5781 Output State Truth Table
DACTRI
OPGND
Output State
0
Normal operating mode.
0
1
Output is clamped via ~6 kΩ to AGND.
1
0
Output is in tristate.
1
Output is clamped via ~6 kΩ to AGND.
LINEARITY COMPENSATION
The integral nonlinearity (INL) of the AD5781 can vary
according to the applied reference voltage span; the LIN COMP
bits of the control register can be programmed to compensate
for this variation in INL. The specifications in this data sheet
are obtained with LIN COMP = 0000 for reference spans up to
and including 10 V and with LIN COMP = 1100 for a reference
span of 20 V. The default value of the LIN COMP bits is 0000.
OUTPUT AMPLIFIER CONFIGURATION
There are a number of different ways that an output amplifier
can be connected to the AD5781, depending on the voltage
references applied and the desired output voltage span.
Unity Gain Configuration
Figure 50 shows an output amplifier configured for unity gain,
in this configuration the output spans from VREFN to VREFP.
A1
6.8k 6.8k
R1
RFB
18-BIT
DAC
VREFPS
VREFPF
VREFP
VREFN
VREFNS
AD5781
1/2 AD8676
AD8675,
ADA4898-1,
ADA4004-1
1/2 AD8676
VREFNF
RFB
INV
VOUT
09
2-
05
4
Figure 50. Output Amplifier in Unity Gain Configuration
A second unity gain configuration for the output amplifier is
one that removes an offset from the input bias currents of the
amplifier. It does this by inserting a resistance in the feedback
path of the amplifier that is equal to the output resistance of the
DAC. The DAC output resistance is 3.4 kΩ. By connecting R1
and RFB in parallel, a resistance equal to the DAC resistance is
available on-chip. Because the resistors are all on one piece of
silicon, they are temperature coefficient matched. To enable this
mode of operation, the RBUF bit of the control register must be set
to Logic 1. Figure 51 shows how the output amplifier is connected
to the AD5781. In this configuration, the output amplifier is in
unity gain and the output spans from VREFN to VREFP. This unity
gain configuration allows a capacitor to be placed in the
amplifier feedback path to improve dynamic performance.
18-BIT
DAC
VREFPS
10pF
VREFPF
VREFP
VREFN
VREFNS
AD5781
1/2 AD8676
AD8675,
ADA4898-1,
ADA4004-1
1/2 AD8676
VREFNF
VOUT
RFB
VOUT
09
2-
05
5
INV
6.8k
R1
Figure 51. Output Amplifier in Unity Gain with Amplifier Input Bias Current
Compensation
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