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參數(shù)資料
| 型號： | AD5790BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VOLT OUT 20BIT 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 2.5µs |
| 位數(shù)： | 20 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ EP（4x5） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
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AD5790
Data Sheet
Rev. D | Page 18 of 28
THEORY OF OPERATION
The AD5790 is a high accuracy, fast settling, single, 20-bit,
serial input, voltage-output DAC. It operates from a VDD supply
voltage of 7 V to 16.5 V and a VSS supply of 16.5 V to -2.5 V.
Data is written to the AD5790 in a 24-bit word format via a 3-wire
serial interface. The AD5790 incorporates a power-on reset
circuit that ensures the DAC output powers up to 0 V with the
VOUT pin clamped to AGND through a ~6 kΩ internal resistor.
DAC ARCHITECTURE
The architecture of the AD5790 consists of two matched DAC
sections. A simplified circuit diagram is shown in Figure 49.
The six MSBs of the 20-bit data-word are decoded to drive
63 switches, E0 to E62. Each of these switches connects one of
63 matched resistors to either the buffered VREFP or buffered
VREFN voltage. The remaining 14 bits of the data-word drive
Switches S0 to S13 of a 14-bit voltage mode R-2R ladder
network.
2R
S0
2R
S1
2R
S13
2R
E62
2R
E61
2R
E0
14-BIT R-2R LADDER
.....................
..........
.........
RR
R
VREFP
VREFN
VOUT
SIX MSBs DECODED INTO
63 EQUAL SEGMENTS
10
239-
05
0
Figure 49. DAC Ladder Structure
SERIAL INTERFACE
The AD5790 has a 3-wire serial interface (SYNC, SCLK, and
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs (see Figure 2 for a
timing diagram).
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK, which can operate at up to 35 MHz. The
input register consists of a R/W bit, three address bits and
20 data bits as shown in Table 6. The timing diagram for this
operation is shown in Figure 2.
Table 6. Input Shift Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19 to DB0
R/W
Register address
Register data
Table 7. Decoding the Input Shift Register
R/W
Register Address
Description
0
No operation (NOP). Used in readback operations.
0
1
Write to the DAC register.
0
1
0
Write to the control register.
0
1
Write to the clearcode register.
0
1
0
Write to the software control register.
1
0
1
Read from the DAC register.
1
0
1
0
Read from the control register.
1
0
1
Read from the clearcode register.
1 X is don’t care.
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| AD5791ARUZ | 功能描述:IC DAC 20BIT SRL 20TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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