VCC = 2.7 V to 5.5 V; al" />
參數(shù)資料
型號(hào): AD5790BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 24/28頁
文件大小: 0K
描述: IC DAC VOLT OUT 20BIT 24LFCSP
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 2.5µs
位數(shù): 20
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ EP(4x5)
包裝: 托盤
輸出數(shù)目和類型: 1 電壓,雙極
Data Sheet
AD5790
Rev. D | Page 5 of 28
TIMING CHARACTERISTICS
VCC = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit1
Unit
Test Conditions/Comments
IOVCC = 1.71 V to 3.3 V
IOVCC = 3.3 V to 5.5 V
t12
40
28
ns min
SCLK cycle time
92
60
ns min
SCLK cycle time (readback mode)
t2
15
10
ns min
SCLK high time
t3
9
5
ns min
SCLK low time
t4
5
ns min
SYNC to SCLK falling edge setup time
t5
2
ns min
SCLK falling edge to SYNC rising edge hold time
t6
48
40
ns min
Minimum SYNC high time
t7
8
6
ns min
SYNC rising edge to next SCLK falling edge ignore
t8
9
7
ns min
Data setup time
t9
12
7
ns min
Data hold time
t10
13
10
ns min
LDAC falling edge to SYNC falling edge
t11
20
16
ns min
SYNC rising edge to LDAC falling edge
t12
14
11
ns min
LDAC pulse width low
t13
130
ns typ
LDAC falling edge to output response time
t14
130
ns typ
SYNC rising edge to output response time (LDAC tied low)
t15
50
ns min
CLR pulse width low
t16
140
ns typ
CLR pulse activation time
t17
0
ns min
SYNC falling edge to first SCLK rising edge
t18
65
60
ns max
SYNC rising edge to SDO tristate (CL = 50 pF)
t19
62
45
ns max
SCLK rising edge to SDO valid (CL = 50 pF)
t20
0
ns min
SYNC rising edge to SCLK rising edge ignore
t21
35
ns typ
RESET pulse width low
t22
150
ns typ
RESET pulse activation time
1
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVCC) and timed from a voltage level of (VIL + VIH)/2.
2
Maximum SCLK frequency is 35 MHz for write mode and 16 MHz for readback mode.
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