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參數(shù)資料
| 型號： | AD5790BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC VOLT OUT 20BIT 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 2.5µs |
| 位數(shù)： | 20 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ EP（4x5） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
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AD5790
Data Sheet
Rev. D | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IN
V
IOV
CC
V
CC
AGND
VSS
VREFN
SD
O
DNC
SDI
N
R
FB
AD5790
TOP VIEW
(Not to Scale)
VOUT
VREFP
RESET
VDD
CLR
LDAC
SYNC
DGND
SCLK
2
1
3
4
5
6
7
18
19
17
16
15
14
13
9
1
0
1
2
8
2
1
2
0
2
3
2
4
10
23
9
-00
5
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. NEGATIVE ANALOG SUPPLY CONNECTION (VSS).
A VOLTAGE IN THE RANGE OF –16.5 V TO –2.5 V
CAN BE CONNECTED. VSS SHOULD BE DECOUPLED
TO AGND. THE PADDLE CAN BE LEFT ELECTRICALLY
UNCONNECTED PROVIDED THAT A SUPPLY
CONNECTION IS MADE AT THE VSS PINS. IT IS
RECOMMENDED THAT THE PADDLE BE THERMALLY
CONNECTED TO A COPPER PLANE FOR ENHANCED
THERMAL PERFORMANCE.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VOUT
Analog Output Voltage.
2
VREFP
Positive Reference Voltage Input. A voltage in the range of 5 V to VDD 2.5 V can be connected.
3, 5
VDD
Positive Analog Supply Connection. A voltage in the range of 7.5 V to 16.5 V can be connected. VDD must be
decoupled to AGND.
4
RESET
Active Low Reset. Asserting this pin returns the
AD5790 to its power-on status.
6
CLR
Active Low Input. Asserting this pin sets the DAC register to a user defined value (see
Table 12) and updates the
DAC output. The output value depends on the DAC register coding that is being used, either binary or twos
complement.
7
LDAC
Active Low Load DAC Logic Input. This is used to update the DAC register and, consequently, the analog output.
When tied permanently low, the output is updated on the rising edge of SYNC. If LDAC is held high during the
write cycle, the input register is updated, but the output update is held off until the falling edge of LDAC. The
LDAC pin should not be left unconnected.
8
VCC
Digital Supply. Voltage range is from 2.7 V to 5.5 V. VCC should be decoupled to DGND.
9
IOVCC
Digital Interface Supply. Digital threshold levels are referenced to the voltage applied to this pin. Voltage range is
from 1.71 V to 5.5 V
10, 21, 22, 23
DNC
Do Not Connect. Do not connect to these pins.
11
SDO
Serial Data Output.
Data is clocked out on the rising edge of the serial clock input.
12
SDIN
Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge
of the serial clock input.
13
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 35 MHz.
14
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the
following clocks. The DAC is updated on the rising edge of SYNC.
15
DGND
Ground Reference Pin for Digital Circuitry.
16
VREFN
Negative Reference Voltage Input.
17, 18
VSS
Negative Analog Supply Connection. A voltage in the range of 16.5 V to 2.5 V can be connected. VSS must be
decoupled to AGND.
19
AGND
Ground Reference Pin for Analog Circuitry.
20
RFB
Feedback Connection for External Amplifier. See the
AD5790 Features section for further details.
24
INV
Inverting Input Connection for External Amplifier. See the
AD5790 Features section for further details.
EPAD
VSS
Negative Analog Supply Connection (VSS). A voltage in the range of 16.5 V to 2.5 V can be connected. VSS must
be decoupled to AGND. The paddle can be left electrically unconnected provided that a supply connection is
made at the VSS pins. It is recommended that the paddle be thermally connected to a copper plane for enhanced
thermal performance.
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