RS R1 R4 R2 50 REF" />
參數(shù)資料
型號: AD660BRZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 5/20頁
文件大?。?/td> 0K
描述: IC DAC 16BIT MONO W/VREF 24-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1,000
系列: DACPORT®
設(shè)置時間: 6µs
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 625mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 167k
AD660
Rev. B | Page 13 of 20
HBE
CONTROL
LOGIC
SER
CLR
LDAC
REF IN
R1
50
R6
R5
R2
R3
RS
R1
R4
R2
50
REF OUT
AD660
AD688
SOUT
VOUT
AGND
SPAN/
BIPOLAR
OFFSET
DGND
–VEE
+VCC
+VLL
10V REF
16-BIT LATCH
16-BIT DAC
16
17
18
19
23
24
20
21
22
13
1
2
3
4
15
01
81
3-
0
13
OUTPUT
0V TO 10V
R2
100
R3
10k
R4
10k
–VS
+VS
14
1
15
2
16
13
11
12
8
10
9
5
A3
A2
A4
A1
4
6
7
3
10k
10.05k
DB1/DB9/
DATADIR
11
LBE/
CLEAR SELECT
DB0/
DB8/
SIN
CS
DB7/
DB15
5
12
14
16-BIT LATCH
Figure 13. Using the AD660 with the AD688 High Precision ±10 V Reference
OUTPUT SETTLING AND GLITCH
The AD660 output buffer amplifier typically settles to within
0.0008% FS (1/2 LSB) of its final value in 8 μs for a full-scale
step. Figure 14 and Figure 15 show settling for a full-scale and
an LSB step, respectively, with a 2 kΩ, 1000 pF load applied.
The guaranteed maximum settling time at 25°C for a full-scale
step is 13 μs with this load. The typical settling time for a 1 LSB
step is 2.5 μs.
The digital-to-analog glitch impulse is specified as 15 nV-s
typical. Figure 16 shows the typical glitch impulse characteristic
at the 011…111 to 100…000 code transition when loading the
second rank register from the first rank register.
+10
0
600
400
200
0
–200
–400
–600
–10
010
20
01
81
3-
01
4
O
UT
P
UT
V
O
L
T
AG
E
(
V
)
O
UT
P
UT
V
O
L
T
AG
E
(
V
)
TIME (s)
Figure 14. 10 V to +10 V Full-Scale Step Settling
01
2
3
4
5
01
81
3-
01
5
O
UT
P
UT
V
O
L
T
AG
E
(
V
)
TIME (s)
600
400
200
0
–200
–400
–600
Figure 15. LSB Step Settling
+10
0
–10
01
81
3-
01
6
O
U
T
P
U
T
VO
L
T
A
G
E
(m
V)
TIME (s)
01
2
3
4
5
Figure 16. Output Characteristics
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