參數(shù)資料
型號(hào)： AD6624
英文描述： LTC1799, LTC6900, LTC6905, LTC6905-XXX, Evaluation Kit
中文描述： AD6624：四通道。 80 MSPS的數(shù)字接收信號(hào)處理器（RSP）的數(shù)據(jù)資料（版本A 9月2日）
文件頁(yè)數(shù)： 33/40頁(yè)
文件大?。?/td> 927K
代理商： AD6624
REV. A
AD6624
–33–
The SCLK can be generated and run up to a maximum of
80 MHz. The serial division bits from this register are not
used for serial port 0. The external SDIV [3:0] pins are used
to determine this for Serial Port 0.
MICROPORT CONTROL
The AD6624 has an 8-bit microprocessor port and four serial
input ports. The use of each of these ports is described sepa-
rately below. The interaction of the ports is then described. The
microport interface is a multimode interface that is designed to
give flexibility when dealing with the host processor. There are
two modes of bus operation: Intel nonmultiplexed mode (INM),
and Motorola nonmultiplexed mode (MNM). The mode is
selected based on host processor and which mode is best suited
to that processor. The microport has an 8-bit data bus (D[7:0]),
3-bit address bus (A[2:0]), three control pins lines (
CS
,
DS
or
RD
, RW or
WR
), and one status pin (
DTACK
or RDY). The
functionality of the control signals and status line changes
slightly, depending upon the mode that is chosen. Refer to
the timing diagrams and the following descriptions for details
on the operation of both modes.
External Memory Map
The External Memory Map is used to gain access to the Channel
Address Space described previously. The 8-bit data and address
registers referenced by the external interface registers can be seen
in Table XI. (These registers are collectively referred to as the
External Interface Registers since they control all accesses to the
Channel Address space as well as global chip functions.) The use
of each of these individual registers is described below in detail.
It should be noted that the Serial Control interface to Chan-
nel 0 has the same memory map as the microport interface
and can carry out
exactly
the same functions, although at a
slower rate.
Access Control Register (ACR)
The Access Control Register serves to define the channel or chan-
nels that receive an access from the microport or Serial Port 0.
Bit 7
of this register is the autoincrement bit. If this bit is a 1,
the CAR register described below will increment its value after
every access to the channel. This allows blocks of address space
such as Coefficient Memory to be initialized more efficiently.
Bit 6
of the register is the broadcast bit and determines how
Bits 5–2 are interpreted. If broadcast is 0, Bits 5–2, which are
referred to as instruction bits (Instruction [3:0]), are compared
with the CHIP_ID [3:0] pins. The instruction that matches the
CHIP_ID [3:0] pins will determine the access. This allows up to
16 chips to be connected to the same port and memory mapped
without external logic. This also allows the same serial port of a
host processor to configure up to 16 chips. If the broadcast bit is
high, the Instruction [3:0] word allows multiple AD6624 chan-
nels and/or chips to be configured simultaneously, independent
of the CHIP_ID[3:0] pins. Ten possible instructions are defined
in Table XII. This is useful for smart antenna systems where
multiple channels listening to a single antenna or carrier can be
simultaneously configured. The x(s) in the table represent “don’t
cares” in the digital decoding.
Table XI. External Memory Map
A[2:0] Name
Comment
111
Access Control Register (ACR)
7:
6:
5–2:
1–0:
7–0:
Auto Increment
Broadcast
Instruction[3:0]
A[9:8]
A[7:0]
110
101
Channel Address Register (CAR)
SOFT_SYNC Control Register
(Write Only)
7:
6:
5:
4:
3:
2:
1:
0:
PN_EN
Test_MUX_Select
Hop
Start
SYNC 3
SYNC 2
SYNC 1
SYNC 0
100
PIN_SYNC Control Register
(Write Only)
7:
Toggle IEN for
BIST
First SYNC Only
Hop_En
Start_En
SYNC_EN 3
SYNC_EN 2
SYNC_EN 1
SYNC_EN 0
6:
5:
4:
3:
2:
1:
0:
011
SLEEP
(Write Only)
7–6:
5:
Reserved
Access Input Port
Control Registers
Serial Read 0
SLEEP
SLEEP 2
SLEEP 1
SLEEP 0
Reserved
D [19:16]
15–8: D [15:8]
7–0:
D [7:0]
4:
3:
2:
1:
0:
7–4:
3–0:
010
Data Register 2 (DR2)
001
000
Data Register 1 (DR1)
Data Register 0 (DR0)
Table XII. Microport Instructions
Instruction
Comment
0000
0001
0010
0100
1000
All chips and all channels will get the access.
Channel 0, 1, 2 of all chips will get the access.
Channel 1, 2, 3 of all chips will get the access.
All chips will get the access.
*
All chips with Chip_ID[3:0] = xxx0 will get
the access.
*
All chips with Chip_ID[3:0] = xxx1 will get
the access.
*
All chips with Chip_ID[3:0] = xx00 will get
the access.
*
All chips with Chip_ID[3:0] = xx01 will get
the access.
*
All chips with Chip_ID[3:0] = xx10 will get
the access.
*
All chips with Chip_ID[3:0] = xx11 will get
the access.
*
1001
1100
1101
1110
1111
*
A[9:8] bits control which channel is decoded for the access.
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