參數(shù)資料
型號(hào)： AD6624
英文描述： LTC1799, LTC6900, LTC6905, LTC6905-XXX, Evaluation Kit
中文描述： AD6624：四通道。 80 MSPS的數(shù)字接收信號(hào)處理器（RSP）的數(shù)據(jù)資料（版本A 9月2日）
文件頁(yè)數(shù)： 36/40頁(yè)
文件大?。?/td> 927K
代理商： AD6624
REV. A
AD6624
–36–
Bit 3
determines if the input consists of a single channel or
TDM channels such as when using the AD6600. If this bit is
cleared, a single ADC is assumed. In this mode, LIA–A functions
as the active output indicator. LIA–B provides the complement of
LIA–A. However, if this bit is set, the input is determined to be
dual channel and determined by the state of the IENA pin. If
the IENA pin is low, the input detection is directed to LIA–A.
If the IENA pin is high, the input is directed to LIA–B. In
either case, Bit 4 determines the actual polarity of these signals.
Bits 2–0
determine the internal latency of the gain detect func-
tion. When the LIA–A, B pins are made active, they are typically
used to change an attenuator or gain stage. Since this is prior to
the ADC, there is a latency associated with the ADC and with the
settling of the gain change. This register allows the internal delay
of the LIA–A, B signal to be programmed.
Addresses 4–7 duplicate address 00–03 for Input Port B
(INB[13:0]).
SERIAL PORT CONTROL
The AD6624 will have four serial ports serving as primary data
output interfaces. In addition to output data, these ports will
provide control paths to the internal functions of the AD6624.
Serial Port 0 (SDIN0) can access all of the internal registers for
all of the channels while Ports 1, 2, and 3 (SDIN1–3) are limited
to their local registers only. In this manner, a single DSP could
be used to control the AD6624 over the Serial Port 0 interface.
The option is present to use a DSP per channel if needed. In
addition to the global access of Serial Port 0, it has preemptive
access over the other serial ports and the microport.
The Serial Output and Input functions use mainly separate
hardware and can largely be considered separate ports that
use a common Serial Clock (SCLK). The Serial Input Port is self-
framing as described below and allows more efficient use of the
Serial Input Bandwidth for Programming. Hence, the state of
the SDFS signal has no direct impact on the Serial Input Port.
Since the Serial Input Port is self-framing, it is not necessary to
wait for an SDFS to perform a serial write. The beginning of a
Serial Input Frame is signaled by a FRAME bit that appears on
the SDI pin. This is the MSB of the Serial Input Frame. After
the FRAME bit has been sampled high on the falling edge of
SCLK, a State Counter will start and enable an 11-bit Serial
Shifter four serial clock cycles later. These four SCLK cycles
represent the “don’t care” bits of the Serial Frame that are
ignored. After all of the bits are shifted, the Serial Input Port will
pass along the 8-bit data and 3-bit address to the arbitration block.
The Serial Word Structure for the SDI input is illustrated in the
table below. Only 15 bits are listed so that the second bit in a
standard 16-bit serial word is considered the FRAME bit. This
is done for compatibility with the AD6620 Serial Input Port.
The shifting order begins with FRAME and shifts the address
MSB first and then the data MSB first.
JTAG BOUNDARY SCAN
The AD6624 supports a subset of IEEE Standard 1149.1 specifi-
cations. For additional details of the standard, please see “IEEE
Standard Test Access Port and Boundary-Scan Architecture,”
IEEE-1149 publication from IEEE.
The AD6624 has five pins associated with the JTAG interface.
These pins are used to access the on-chip Test Access Port and
are listed in the table below. All input JTAG pins are pull-up,
except for TCLK which has a pull-down.
Table XIV. Boundary Scan Test Pins
Name
Pin Number
Description
TRST
TCLK
TMS
TDI
TDO
67
68
69
72
70
Test Access Port Reset
Test Clock
Test Access Port Mode Select
Test Data Input
Test Data Output
The AD6624 supports the op codes as shown below. These
instructions set the mode of the JTAG interface.
Table XV. Boundary Scan Op Codes
Instruction
Op Code
IDCODE
BYPASS
SAMPLE/PRELOAD
EXTEST
HIGHZ
CLAMP
001
111
010
000
011
100
The Vendor Identification Code can be accessed through the
IDCODE instruction and has the following format.
Table XVI. Vendor ID Code
MSB
Version
Part
Number
Manufacturing
ID #
LSB
Mandatory
0000
0010
0111
1000
1100
000 1110 0101
1
A BSDL file for this device is available; please contact Analog
Devices, Inc. for more information.
FRAME
X
X
X
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SDI
CLKn
FRAME
X
t
SSI
t
HSI
Figure 45. Serial Port Control Timing
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6624A 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
AD6624AABC 制造商:Advanced Micro Devices 功能描述:
AD6624AABCZ 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
AD6624AS 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP)
AD6624AS/PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
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